msp430f5529 Clock Source

There is also a module clock source: Modosc, generates MODCLK clock source signal, Typically only the Flash control module and the ADC12 module are serviced.

The module is automatically closed when not in use, and when any module makes use of the clock source, the Modosc does not need to be enabled to respond to the request. The MODCLK in 430f5529 is 5MHZ. The msp430f5529 has multiple clock sources, and many modules have a freely selectable clock source. In addition, because the system power consumption is proportional to the operating frequency, in some cases, by selecting the lower frequency clock source, it can effectively reduce the power consumption under normal operating conditions. Although the function library hal_ucs.c/h, there are full of various control functions, but I think for this chapter or register direct operation is relatively simple, because the function is too short, too many. 3.1 Unified Clock System ( UCS ) Introduction toUnified Clock System,ucs. A reasonable configuration of the clock can achieve the purpose of balancing the system and reducing power consumption. MSPF5529 The clock system contains 5 a clock Source: ① LFXT1The external low frequency oscillation source, 32.768KHZ, can be used as the reference source of FLL; ② XT2External high-frequency oscillation source, 4MHZ; ③ VLO ( Internal very low )Internal low-frequency oscillator source, typical 10KHZ, the accuracy of general; ④ RefoInternal low-frequency reference source, 32.768KHZ, is often used as the reference frequency of the phase-locked loop FLL, the accuracy is very high, do not use the power supply, its settings often refer to the setting of the LPM mode; ⑤ DCO ( Internal digitally-controlled )Internal digital control oscillation source, usually through the FLL to set; very useful, very important, will be detailed later）   typically used 3 all of them from the above 5 Source of signal: ① ACLK ( Auxiliary Clock )Auxiliary clock, its clock source can be controlled from XT1, Refoc, VLO, DCO, Dcoclkdiv, XT2 inside the software control. The dcoclkdiv is obtained by the DCO by 1, 2, 4, 8, 16 or 32. Note that the ACLK can also be divided by 1, 2, 4, 8, 16, or 32 again. ② MCLK ( Master Clock )The main clock, with the same characteristics as the ACLK. ③ SMCLK ( Subsystem Master Clock )subsystem clock, which has the exact same characteristics as ACLK. 3.2 UCS the operating instructions                     The default clock condition for power-on IS (must be remembered!!!!!) ): ACLK :XT1 (invalid, low-frequency mode switched to REFO, other conditions switched to DCO) MCLK: Dcoclkdiv SMCLK :Dcoclkdiv                     in addition,The reference source of the FLL is default XT1; If the pins of the connection XT1 and XT2 do not have the Pxsel settings, then the two clock sources are invalid; refoclk, VLOCLK, DCOCLK are available by default; once the system is stable, DCOCLK default is 2.097152MHZ , FLL default 2 Divide, then MCLK and the SMCLK the frequency is 1.048576MHZ . (Experiment three will mention how to calculate)                               In addition, the system reset, the system operation mode LPM selection will have a certain impact on the UCS, there are too many restrictions, specific reference TI official information UCS section. LPM and system reset are described in the next chapter. a simple summary of the operating instructions: (The following basic is nonsense, understand it) ①The choice of Vlo is the simplest, and there is no need to take into account other circumstances; ②The choice of Refo, need to refer to different working modes, there are many restrictions; ③XT1 and XT2 have the same characteristics. When using, not only to configure the pin connected to it, but also to configure the capacitance, but also note that it is operating in the low-frequency or high-frequency mode. Moreover, there are different requirements under different working modes; ④dCO as a numerical control oscillator, its frequency adjustment can not only be set by itself, but also through the FLL phase-locked loop set; ⑤The FLL phase-locked loop is a flexible choice for the conversion frequency. It can set the reference frequency, can also choose the frequency division number, but also can be closed directly to achieve the purpose of reducing power consumption; ⑥UCS system with clock signal error protection mechanism; ⑦Where there are strict timing requirements, select a high-precision clock source, and do a good job of the FLL and DCO modulation settings; ⑧Clock control charts in different modes (some clock sources are forbidden): (Just pay attention when you need to, check the table)

3.3 UCS Register Control Operation             There are 10 groups of 16-bit read-write registers for UCSCTL0-UCSCTL9. Word and byte operations are also supported, i.e. UCSCTL0 includes Ucsctl0_h and ucsctl0_l. Note: all markings " Reserved "bit, if not intentionally declared, when read back, press the 0 processing. UCSCTL0:

DCO : The DCO frequency shot selection. Select dCO's cadence and adjust automatically during the FLL operation (due to changes in mod bit). The 5 control bits of DCO divide the DCO frequency chosen by dcorselx into 32 equal parts, spaced approximately 8%.

MOD :Modulation bit counter. Select the modulation type and all mod bits are automatically adjusted during the FLL run without user intervention. UCSCTL1:

        Dcorsel :DCO Frequency Range Selection Dismod :The modulator is forbidden to enable the bit. 0-Enable modulator, 1-inhibit modulator. UCSCTL2:

F LLD : prescaler (i.e. Fdco frequency divider). 000-1-Way, 001-2-way, 010-4-divided,

011-8, 100-16, 101-32, 110, and 111 are all standby, and the default is 32. Flln :Multiplier coefficients. Set the multiplier value N,n must be greater than 0, if flln=0, then n is automatically set to 1. UCSCTL3:

      

Selref :FLL reference Clock Selection.                           000-xt1,001-to be used, the default is Xt1,010-refo,101-xt2, the rest is to be used, the default is Refo. Fllrefdiv :FLL Reference Clock Divider. 000-1, 001-2, 010-4, 011-8, 100-12, 101-16, 110 and 111 are all standby, and the default is 16. UCSCTL4:

SELA : ACLK clock Source Selection.

000-xt1,001-vlo,010-refo,011-dco,100-dcoclkdiv,101-xt2 valid for XT2, otherwise dcoclkdiv 110, 111 reserved for later use. The default is XT2CLK when XT2 is active, otherwise the default is Dcoclkdiv SELS :SMCLK clock Source Selection. Set the same SELA Selm :MCLK clock Source Selection. Set the same SELA UCSCTL5:

DIVPA : ACLK external effective output divider 000-1-way, 001-2-way, 010-4-frequency,

011-8, 100-16, 101-32, 110, and 111 are all standby, and the default is 32. DIVA :ACLK clock source divider, set with DIVPA divs :SMCLK clock source divider, set with DIVPA DIVM :MCLK clock source divider, set with DIVPA UCSCTL6:

xt2drive : XT2 oscillator current drive capability adjustment

00 minimum current consumption. The XT2 oscillator works in 4MHz to 8MHz ... Xt2bypass :XT2 Bypass selection 0-xt2 from internal clock (using external crystal) 1-XT2 from external pin input (bypass mode) Xt2off :Turn off the XT2 oscillator 0-when the XT2 pin is set to XT2 function and is not set in bit bypass mode, XT2 is turned on, 1-XT2 is turned off when XT2 is not used as a clock source and is not used as the FLL reference clock. XTS :XT1 operating mode selection 0-Low Frequency mode (XCAP defines capacitance between Xin and xout pins) 1-High frequency mode (Xcap bit not used) XCAP :Oscillator load Capacitance Selection Smclkoff :SMCLK off control bit 0-SMCLK open 1-SMCLK off Xt1off :With Xt2off UCSCTL7:

XT2OFFG : XT2 when the error occurs, while the OFFIFG will also be set, requiring the software to clear the zero.

XT1HFOFFG :High-frequency operating mode XT1 error when the position, while the OFFIFG will also be set, the need for software zeroing. XT1LFOFFG :Low-frequency operating mode XT1 error when the position, while the OFFIFG will also be set, the need for software zeroing. DCOOFFG :DCO is set when an error occurs, but when dco=1 or 31 o'clock is set, the OFFIFG will also be set, requiring the software to be zeroed.

Experiment One: configure MCLK and smclk as refoclk,vloclk ( oscilloscope measurement required)

/* REFOCLK and VLOCLK is the chip provided by default, as long as the chip works, the two clocks will work, so the clock configuration is very simple, only need to modify the UCSCTL4, Sels and Selm configured to the corresponding options VLOCLK or REFOCLK can */ #include void Main( void) {wdtctl = Wdtpw+wdthold; P1sel |= bit0;//Declaration has a special function, will not be used as normal I/O p1dir |= bit0;//aclk output, used to measure aclk frequency, external frequency measurement p2sel |= BIT2; P2dir |= bit2;//smclk output P7sel |= BIT7; P7dir |= bit7;//mclk with output//UCSCTL4 = ucsctl4& (~ (sels_7| selm_7)) | sels_1| Selm_1; Configure SMCLK and mclk to vloclk UCSCTL4 = ucsctl4& (~ (sels_7| selm_7)) | sels_2| selm_2; Configure SMCLK and MCLK to refoclk/* ucsctl4& (sels_7| SELM_7)) This statement is equivalent to first sels and Selm 0 */ while(1);}

msp430f5529 Clock Source