Multiplier Design experiment

Assume that if the Ain and bin of the chip are oxffff at MHz, 16 clock cycles are required to obtain the multiplication result. The data throughput of the chip at MHz is: 200 MHz/16 = 12.5hmz

The IO Interface is defined as follows:

CLK input clock signal, 50 m

Rst_n input reset signal, effective at low level

Start input enabling signal. If the value is 0, the signal is invalid. If the value is 1, the system reads the multiplier and the received multiplier. When the signal is changed from 0 to 1, the system performs a multiplication operation on the current Ain and bin, to perform the next operation, you need to lower the signal and increase it.

Ain input a (multiplier), with a data Bit Width of 16 bits

Bin input B (multiplier), with a data width of 16 bits;

Yout output product output, whose data width is 32bit;

Done output valid flag to maintain a high clock cycle when it is effective. If the value is 1, the multiplication operation is completed, and the data on the yout port is stable, the final product is obtained. If the value is 0, the multiplication operation is not completed, and the yout data is unstable.

Module mux16 (CLK, rst_n, start, Ain, bin, done); input CLK; input rst_n; input start; input [15:0] Ain; input [15:0] bin; output [31: 0] yout; output done; Reg [15:0] Areg, breg; Reg [31: 0] yout_r; Reg done_r; Reg [4:0] I; // Shift count register  //--------------------------------- Always @ (posedge CLK or negedge rst_n) If (! Rst_n) I <= 5'd0; Else     If (Start & I <5 'd17) I <= I + 1 'b1; Else     If (! Start) I <= 5'd0; //--------------------------------- Always @ (posedge CLK or negedge rst_n) If (! Rst_n) done_r <= 1 'b0; Else    If (I = 5 'd16) done_r <= 1 'b1; Else   If (I = 5 'd17) done_r <= 1 'b0;

 assign done = done_r;  // --------------------------------   // use the dedicated register to perform the shift accumulate Multiplication operation  always @ (posedge CLK or negedge rst_n) Begin  If  (! Rst_n) Begin Areg <= 16 'h0000; breg <= 16 'h0000; yout_r <= 32 'h0000 _ 0000; end  else   If  (start) Begin  If  (I = 5 'd0) Begin Areg <= ain; breg <= bin; end  else   If  (I> 5' D0 & I <5' D16) beign  If  (Areg [I-1]) 

Yout_r = {1 'b0, yout [30: 15] + breg, yout_r [14:1]};ElseYout_r <= yout_r> 1; EndElse If(I = 5 'd16 & Areg [15])
 

 
Yout_r [31: 16] <= yout_r [31: 16] + breg; endend
 

Assign yout = yout_r;

Endmodule