My FPGA Learning Journey (02)--Experiment lit LED light

For Quartus, you can use the help from Quartus, which has a full set of tutorials.

Links to Chinese web tutorials (link to Altera Chinese website, click to view)

1. Quartus II Software Design series: Foundation
2. Schematic design in Quartus II software
3. Signaltap II Embedded Logic Analyzer
4. Using the Nios II processor
5. System console
6. Nios II Processor Development software: Design process
7. Nios II Processor Development software: MMU and MPU

Whether it is English help or online Chinese course, their premise is that you are basic , these tutorials will teach you how to use our Quartus suite, as for Verilog you should implement learning, processor basic support you should listen to understand. The basics are not in their duties, this is understandable.

This is my first experiment to use a key to control an LED light, using a schematic input.

1. Click File–> New Project Wizard to create a new item

2. Enter the project catalog

Quartus required to create a new empty directory to save the project file, the path cannot have Chinese and white space.

In addition, the project name and the top-level module name are generally consistent with the catalog name.

The name of the third row must be the same as the top-level module name when using HDL input, or compile an error, here is the schematic input, temporarily can regardless of

3. Add additional files to the project

If you have already written the Verilog file, and the top-level module name is the same as the project requirements, add the other file path here, we are left blank here.

4. Select the model of the FPGA.

The FPGA I used on the AX301 board belonged to Cyclone IV ep4ce6fc8n,

Cyclone IV is Altera's low-end series, with the Cyclone IV in two series, where the E-series is without high-speed transceivers, while the GX series has a high-speed transceiver. In addition the end of N represents a lead-free process, L represents a low voltage.

As can be seen from the table below, the chip has 6,272 LE units, 180 user pins, and 2 phase-locked loops.

5. Other tools

Quartus can use other tools to complete the FPGA design, the first is the selection of the integration, the second is the choice of simulation tools, the fourth is board-level selection.

Here we do not, do not choose to leave blank can also.

6. Project Overview

To confirm that the first few choices are correct, just look at it.

7. After the project is completed, click File–-> New to create a new schematic file

8. Schematic Editor

Double-click on the schematic blank, pop up the following dialog box, enter not in the search box, indicating the selection of non-gate.

The same and2 is the two input with the door, Or2 is or door. Be careful to look at the symbols of the other originals so that you don't know when to use them.

After the input is done, the arrow buttons indicate selection, the small hand is the drag, and the wire, bus, and several drawing buttons (blocks, ellipses, etc.)

If the input or output is a bus, you need to change the name to led[7..0] instead of led[7:0].

In addition to input and output, symbols, the wire can also be named (right click on the wire, to rename).

Quartus and Protel like the use of network markings to connect wires and buses, such as a bus named a[3..0], and then the four other wires named A[3], a[2], a[1], a[0], you can achieve their connection.

9. Assigning FPGA Pins

This project uses two pins, a button and an LED to view the user manual, my user manual is as follows

Here I choose to use LED0 and KEY1, need to remember two pin names G15 and E15. (-?-;)

After assigning pins

10. Project Settings

This piece of EP4CE6F17C8 chip can be connected to multiple clocks, but because the chip has a PLL (phase-locked loop, for frequency division, octave, change the clock phase), for beginners, the phase-locked loop is enough to not need to use multiple clocks, so the chip on the more out of the clock pin is used on the button, This needs to be set.

Under Project–> settings, click Device in the upper-right corner ...

Locate the Device and Pin Options page and set the multi-use PIN as the normal pin

Set the unused pins to three states, click OK

Because the last time we did not set pin-corresponding pins, although also generated the SOF file, but this file can not be used. Need to compile the project again.

Review the warnings, errors, and prompts after compiling. Here is a hint that there is no timing constraint file, beginners do not bother.

Warning note there is no clock, the clock must be used in the timing logic, here is a simple combination of logic, useless to use the clock

The top tip is the setup information for multi-use pins.

The principle of assigning pins has changed and the assigned pin names are shown on the figure

11.usb-blaster driver Installation

Black Gold manual and video repeatedly stressed, do not live Plug and unplug Jtag cable (that is, the group of 10pin Line), because the low-end Cyclone IV without clamp diode, live pluggable Jtag port may burn out the FPGA, my process is to first close the development Board switch, connected to the two jtag, the USB -blaster the other end of the USB cable, and then connect the usb-blaster to the computer, connect the Development Board power, and finally open the Development Board power switch.

Connect the Usb-blaster to the computer and find the system and security >> system >> Device Manager in the Control Panel.

A device with a yellow exclamation mark is selected in Device Manager without the driver installed, select Update Driver, manually specify the drive folder path to C:\altera\13.0sp1\quartus\drivers\usb-blaster (this assumes the installation path is C drive).

The Device Manager looks like this when the driver is installed.

12. Burn Write to SRAM

Some of the books introduced in the FPGA should mention that FPGA-based SRAM technology, SRAM can be repeatedly configured, the process of the configuration of FPGA programming, so that it becomes the function we want, simple programming may be like this project only use a few doors, Perhaps the complex point is to write a digital tube or screen driver.

Later, the FPGA can be configured as a processor, quartus in the Qsys or sopcbuilder can easily generate a processor's HDL code, known as the NIOS processor is far less complex than ARM, can be used for embedded processor learning.

Connect the necessary cables to the Development Board and enter the burn-write step below.

Set Usb-blaster

Click AddFile ... Select the SOF file for the Project Output_files directory (mine is test_project.sof). Click the Start button to start the burn, the picture is successful.

Since the SOF file burned to the SRAM power loss will be lost. Therefore, the SOF file user debugging, JIC files and POF files can be fixed on Altera's dedicated configuration chip EPCS, enabling offline operation.

Keep the status of the connected computer, test the button, whether the LED is lit when pressed.   Did you succeed? ('? ') )

Power off the board, unplug the Usb-blaster and computer, remove the power cord from the board, and finally disconnect the JTAG port.

My FPGA Learning Journey (02)--Experiment lit LED light