Niosii/F data cache and tightly-coupled memory

This problem has plagued me for N years (2 days )...

IOWR writes data to summarize the depressing problem.

Http://www.cnblogs.com/crazybingo/archive/2010/11/26/1888731.html

 

In the previous blog, I raised a question.

# Define led_data * (volatile unsigned char *) led_pio_base

Direct operations do not work, but you can execute them after adding printf (). I have never figured out this problem. Now I have finally solved it...

Finally, under the guidance of my brother's reluctance, I finally learned About Baidu Google and the manuals and books .....

The following is a graphic example: Handbook + zlg_book + BMP + TXT to solve the problem.

When you create a CPU in the system, the content of the system is different:

The following is the content of the question,

Data cache is blocked and there is no data cache Problem

The following is the content of the question: (you can disable it here to avoid a series of problems)

The problem lies in the 32-byte date cache (data cache) of 2 kb for the CPU.

 

The data cache is equivalent to the computer's Level 1 cache and level 2 cache to improve the system speed, because it can send data and receive data all the time.

According to the explanation about cache and tightly-coupled memory on the nioii processor Handbook:

 

It can be seen that the ldio/stio commands explicitly specify the 31st-bit address to provide an optional method for the bypass data cache.

If 31st is the address height-1-: The data cache area is bypassed

If 31st indicates that the address is pulled down-0-: The data cache is opened

Therefore, you can use the software to disable the data cache in the Nios/F.

31st-bit addresses can only be used inside the processor, so the maximum address space is only 31 bits, and2 GB addressing space

Later, we will talk about,It is also a 31-bit and 2 GB addressing space for the Nias/E and Nias/s.To facilitateCodePort

The following is an excerpt from zlg'sBasic tutorial on embedded systems with the help of the systemP68 and p69:

"Both the instruction master port and the data master port in the niosii structure support high-speed cache.

High-speed cache uses in-chip Storage

You can port commands and data cache commands and data caches in the Nios/F program at runtime, but you can use software to bypass the data cache.

The high-speed cache for the out-of-town part of the niosii processor is optional in the system's "systems" bulider. It depends on your requirements for the system's Champions League storage performance.

The data instruction cache of the Nios II processor is optional.

Niosii high-speed cache improves the efficacy of myocardial infarction

(1) The conventional memory is located outside the chip, and is a time> In-chip memory.

(2) The maximum and key performance command sequence length for cyclic execution is smaller than the Instruction Cache speed.

(3) the maximum data size of key performance data is smaller than the data cache speed.

Disadvantages of High-speed cache for niosii

(1) high-speed cache has no advantage when only in-chip memory is used

(2)Program2 kb cycles, 1 kb cached at high speed, no effect (above (3 ))

(3) making program execution time unpredictable

The core of the nio ii processor supports a high-speed cache bypass mechanism called 31, which bypasses the high-speed cache based on the maximum valid bit value.

The core addresses of the niosii are limited to 31 and 2 GB.

"

At this point, I suddenly realized that my other development board was running because it was too difficult to draw a picture. Therefore, I have been using NIOS/E and NIOS/s, I keep writing like this

I have never encountered any problems in this writing. The reason is that the data cache zone does not exist for the Nias/E and Nias/s, and bit31 is invalid.

However, there is a data cache zone in the niosio/F, and bit31 is valid. Therefore, if you want to directly use address ing, you must block the highest bit.

# Define led_data * (volatile unsigned int *) (led_pio_base | (1 <31 ))//Increase bit31

In this way, you can operate

I added printf () to led_data = 1,

Because the data sent to led_data is stored in the data cache, It is not processed in a timely manner.,

I personally think that printf is being operated on by a computer. This colleague happens to have fpga cpu idle, so the cache zone is released and I/O is valid (if there is something missing, please ask anyone who can see it. Thank you)

The following shows the SPI register ing method of my master.

Bypass cache is required for register ing in the Nios/f. Otherwise, errors may occur...

.........

# Define led_data * (volatile unsigned int *) (led_pio_base | (1 <31 ))

Int main ()
{
Unsigned char table [] = {0x00,0x01,0x02,0x03 };
Unsigned char I;
Printf ("time is flying... \ n ");
Printf ("I want to vomit blood... \ N ");
While (1)
{
For (I = 0; I <4; I ++)
{
Led_data = table [I];
Delay_ms (500 );
}
}
Return 0;
}

However, the cache has a defect, that is, the data cannot be processed in a timely manner, and the execution time of the Code becomes uncertain, reducing the real-time performance.

There is a better solution, that is, tigtly-coupled memory, tightly coupled latches: it is a fast SRAM next to the kernel.

(1) Improved system performance

(2) ensure that the time for installation and storage of commands or data is determined

The tightly coupled storage device improves the performance of niosii and provides predictable real-time response. It has the following features:

(1) performance is similar to high-speed cache

(2) software can store code or data with critical performance in tightly coupled memory.

(3) Determination of code execution-the time for loading and storing commands or data is predictable

Added support for Coupled memory for instruction and data access after niosii

If the application and memory need to be small and can be fully implemented in a chip, you can use a tightly coupled coupler dedicated to code and data,But how to use pinch ???

Anyway, the problem is solved. The ing between the static address master end and the slave end is almost known ....

Develop the habit of bit31 operations for cache to facilitate Transplantation

Let's sum up a little bit. It looks good at handbook !!!

Discover problems -- ask questions -- fruitless -- read handbook -- while (1) {calm, the problem can always be solved .........}