NOR Flash Erase and Principle analysis (i)

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Author: User

1. NOR FLASH's Brief introduction

Nor FLASH is a very common kind of memory chip, the data power loss will not be lost. Nor flash supports execute on chip, which means that programs can be executed directly on the flash slice (meaning that programs stored on nor flash do not need to be copied to RAM to run directly). This is not the same as NAND flash. Therefore, in an embedded system, nor Flash is well suited as the boot program's storage medium. Nor flash reads similar to RAM (the data bus is able to give the correct information when the data is provided), but it cannot be written directly. Writing to nor flash requires a specific sequence of commands to follow, Finally, the control unit inside the chip completes the write operation.

From the supported minimum access units, nor flash is generally divided into 8-bit and 16-bit (of course, there are also many nor flash chip support 8-bit mode and is 16-bit mode, the specific operation mode through the specific pin selection).

For a 8-bit nor flash chip, or a chip that works in 8-bit mode, an address corresponds to a byte (8-bit) of data. For example, a 8-bit nor flash, assuming a capacity of 4 byte. The chip should have 8 data signals d7-d0 and 2 address signals, a1-a0. Address 0x0 corresponds to the No. 0 byte, the address 0x1 corresponds to 1BYTE, the address 0x2 corresponds to the 2nd byte, and the address 0x3 corresponds to the 3rd byte. To a 16-bit NOR flash chip, or working in 16-bit mode, an address corresponds to a half-word (16-bit) data. For example, a piece of 16-bit NOR FLASH, assuming that it has a capacity of 4 byte. That chip should have 16 data signal lines D15-D0 and 1 address signal A0. Address 0x0 corresponds to the No. 0 Half-word inside the chip, and the address 0x1 corresponds to the 1th Half-word inside the chip

Flash is generally divided into many sector, each sector includes a certain number of storage units. For some large volume of flash, but also divided into different banks, each bank including a certain number of Sector.flash erase operations are generally sector, Bank or the entire flash unit.

When writing to flash, each bit can be programmed from 1 to 0, but not 0 can be changed to 1. To ensure the correctness of the write operation, the erase operation is performed before the write operation is performed. The erase operation will flash a sector, The value of a bank or the entire flash is modified to 0xFF. This allows the write operation to be completed correctly.

Since nor Flash has no local bad zone management, the software or driver must take over the problem once the storage block has been corrupted, otherwise it may cause an exception to the device. When you unlock, erase, or write to nor FLASH chunks, special instructions first write to the first page of the mapped memory area. Then the flash memory chip will provide a list of available instructions to the entity driver, which is made up of a generic Flash interface (CommON flash memory Interface, CFI) defined. Unlike ROM for random access, nor flash can also be used on storage devices, but the write speed of nor flash is generally much slower than NAND flash.

2. NOR Flash's Burning method

The following, if no special instructions, the processor refers to the ARM processor, flash refers to NOR flash. In addition, byte refers to the 8-bit data unit, Half-word represents the 16-bit data unit, and Word represents the 32-bit data unit.

2.1 Processor Addressing

Arm can be said to be the most popular 32-bit embedded processor. Here, just mention the address of the ARM processor, and make an exhibition pad for the back. From the processor's point of view, each of the addresses in the system corresponds to a byte data unit. This is the same as many other processors.

2.2 Processor and nor flash hardware connection

From the front, we know that from the processor's point of view, each address corresponds to a byte unit of data. Instead, each address of nor FLASH may correspond to a byte data unit, or it may correspond to a Half-word data unit. So in hardware design, When connecting the ARM processor and NOR Flash, the address signal must be specially handled according to the actual situation.

If the external expansion of the ARM processor is 8-bit nor FLASH, the connection of the data cable and address line should be shown in 1. We can see that the data signal of the processor D0-D7 and flash data signal D0-d7 is the corresponding connection, the address signal of the processor A0-an and nor flash address signal a0-an is also the corresponding connection.

If the ARM processor external extension is 16-bit nor FLASH, the address line must be misaligned connection. Figure 2 gives a connection to an ARM processor and a 16-bit NOR flash. 2, the data signal of the ARM processor D0-D15 and the data signal of FLASH D0-D15 is one after the other. The address signal of the ARM processor and the address signal of NOR Flash are misaligned, ARM's A0 floating, arm's A1 connection flash a0,arm A2 connection Flash A1, and so on. The reason for the need for a misaligned connection is that each address of the ARM processor corresponds to a byte data unit, and the 16-bit FLASH Each address corresponds to a half-word (16-bit) data unit. In order to maintain a match, the connection must be staggered. Thus, the lowest bit of the address signal sent from the ARM processor is A0 to 16-bit Flash.

Additional notes:

    • In general, the ARM processor internally to set the appropriate register, to tell the processor external expansion of the width of the Flash (8-bit/16-bit/32-bit). This way, the processor knows how to read the data correctly from flash when it is accessed;
    • Some ARM processors can set the location of the dislocation. For the support software to choose the address dislocation of the processor, when connected to 16-bit Flash, the hardware can not need to address line dislocation. When the reader design, please refer to the MCU data sheet, the manual, to avoid unnecessary trouble;
    • If the processor supports internal set address dislocation, in the actual access, the address is actually sent in the MCU internal dislocation processing, its role is equivalent to the dislocation of the hardware connection.

The above description may be abstract, let's look at 2 examples of ARM processors accessing 16-bit Flash:

Example 1:arm processor needs to read a byte from address 0x0

    1. The ARM processor sends the signal 0x0 on the address line an-a0;
    2. 16-bit Flash in its own address signal an-a0 see the address is 0x0, and then the address 0x0 corresponding to the 16-bit data unit output to d15-d0;
    3. The ARM processor knows that the 16-bit Flash is being accessed and reads the required byte data from the D7-D0.

Example 2:arm processor needs to read a byte from address 0x1

    1. The ARM processor sends the signal 0x1 on the address line an-a0;
    2. 16-bit Flash in its own address signal an-a0 see the address is still 0x0, and then the address 0x0 corresponding to the 16-bit data unit output to d15-d0;
    3. The ARM processor knows that the 16-bit Flash is being accessed and reads the required byte data from the D15-D8.
2.3 From the software point of view ARM processor and NOR FLASH connection

The connection between ARM processors and Flash is understood from a software perspective. For 8-bit flash connections, it's good to understand that because each address of the ARM processor and 8-bit Flash corresponds to a BYTE data unit. So the address connection is undoubtedly one-to-another. If ARM The processor is connected to the 16-bit processor, since each address of the ARM processor corresponds to a BYTE unit of data, and each address of 16-bit FLASH corresponds to a half-word 16-bit data unit. So there's no doubt that ARM processor Access 1 6-bit the processor, the address must be staggered. When writing flash drivers, we don't need to know if the address mismatch is implemented by hardware, or by setting the internal registers of the ARM processor, just remember 2 points:

    1. When the ARM processor accesses 8-bit Flash, the address is the corresponding one;
    2. When the ARM processor accesses 16-bit Flash, the address must be misplaced.
2.4 8-bit FLASH Burn Write driver Example-hy29f040

HY29F040 is a modern company's 8-bit nor flash. In this section, we use this chip as an example of how to operate on 8-bit NOR Flash.

The capacity of the hy29f040 is 512k-byte with a total of 8 sector, each sector capacity is 64k-byte. The chip supports sector erase, entire erase, and write manipulation with BYTE as the base unit. The command definition for hy29f040 is shown in table-1.

Let's take a look at how to implement basic erase and programming operations. In the descriptions later in this section, we used the following 2 definitions:

U32 sysbase;          This variable is used to indicate the start address of FLASH, # define SYSADDR8 (Sysbase, offset)    ((volatile u8*) (sysbase) + (offset))   //used to facilitate the specified FALSH Address to operate

Macro SYSADDR8 defines a BYTE (8-bit) pointer with the address (sysbase + offset). Assuming that the start address of Flash is 0x10000000, if you want to write 0xAB to the first byte of Flash, you can use the following code:

*SYSADDR8 (0x10000000, 0x1) = 0xAB;

Attention:

In the description later in this section, Sysbase represents the start address of the flash, and offset in SysAddr8 represents the byte offset from the flash start address. Offset is also 8-bit The address that Flash sees on its own address signal an-a0.

A. Erase operation of Whole piece

A total of 6 cycles of bus write operations are required for the entire erase operation:

    1. Write 0xAA to FLASH address 0x5555;
    2. Write 0x55 to FLASH address 0x2aaa;
    3. Write 0x80 to FLASH address 0x5555;
    4. Write 0xAA to FLASH address 0x5555;
    5. Write 0x55 to FLASH address 0x2aaa;
    6. Write the 0x10 to the FLASH address 0x5555.

The corresponding code:

*SYSADDR8 (sysbase, 0x5555) = 0xAA;    Write the value 0xAA to the FLASH address 0x5555*sysaddr8 (sysbase, 0x2aaa) = 0x55;    Writes the value 0x55 to the FLASH address 0x2aaa*sysaddr8 (sysbase, 0x5555) = 0x80;    Writes the value 0x80 to the FLASH address 0x5555*sysaddr8 (sysbase, 0x5555) = 0xAA;    Write the value 0xAA to the FLASH address 0x5555*sysaddr8 (sysbase, 0x2aaa) = 0x55;    Writes the value 0x55 to the FLASH address 0x2aaa*sysaddr8 (sysbase, 0x5555) = 0x10;    Writes the value 0x10 to the FLASH address 0x5555
B. Sector Erase operation

A total of 6 cycles of bus writes are required for the sector erase operation:

    1. Write 0xAA to FLASH address 0x5555;
    2. Write 0x55 to FLASH address 0x2aaa;
    3. Write 0x80 to FLASH address 0x5555;
    4. Write 0xAA to FLASH address 0x5555;
    5. Write 0x55 to FLASH address 0x2aaa;
    6. Write the 0x30 to the address of the SECTOR that you want to erase.

The corresponding code:

*SYSADDR8 (sysbase, 0x5555) = 0xAA;    Write the value 0xAA to the FLASH address 0x5555*sysaddr8 (sysbase, 0x2aaa) = 0x55;    Writes the value 0x55 to the FLASH address 0x2aaa*sysaddr8 (sysbase, 0x5555) = 0x80;    Writes the value 0x80 to the FLASH address 0x5555*sysaddr8 (sysbase, 0x5555) = 0xAA;    Write the value 0xAA to the FLASH address 0x5555*sysaddr8 (sysbase, 0x2aaa) = 0x55;    Writes the value 0x55 to the FLASH address 0x2aaa*sysaddr8 (sysbase, addr) = 0x30;     Writes the value 0x30 to the address of the SECTOR to erase
C. Byte Erase operation

Writing a byte of data into Flash, requires 4 cycles of the bus write operation:

    1. Write 0xAA to FLASH address 0x5555;
    2. Write 0x55 to FLASH address 0x2aaa;
    3. Write 0xA0 to FLASH address 0x5555;
    4. Writes the programming data (BYTE) to the corresponding programmatic address.

The corresponding code:

*SYSADDR8 (sysbase, 0x5555) = 0xAA;    Write the value 0xAA to the FLASH address 0x5555*sysaddr8 (sysbase, 0x2aaa) = 0x55;    Writes the value 0x55 to the FLASH address 0x2aaa*sysaddr8 (sysbase, 0x5555) = 0xA0;    Writes the value 0xA0 to the FLASH address 0x5555*sysaddr8 (sysbase, addr) = data;      Writes a byte data to the address at which it is due
2.5 16-bit FLASH Burn Write driver Example-sst39vf160

SST39VF160 is a 16-bit nor FLASH of SST company. In this section, we take sst39vf160 as an example of how to operate on 16-bit NOR Flash. The operation of 8-bit Flash is well understood, but the operation of 16-bit Flash is much more obscure. I try to describe it clearly.

The capacity of the sst39vf160 is 2m-byte, which consists of 512 sector, each sector capacity is 4k-byte. The chip supports sector erase, whole piece erase and write manipulation with Half-word as the basic unit. The command definition for sst39vf160 is shown in table 2. In table 2, because all commands are defined from the perspective of Flash. Therefore, all addresses are half-word addresses, referring to the address 16-bit Flash sees on its own address signal an-a0.

In the descriptions later in this section, we used the following 2 definitions:

U32 sysbase;          This variable is used to indicate the start address of FLASH, # define SYSADDR16 (Sysbase, offset)  ((volatile u16*) (sysbase) + (offset))  //used to facilitate the specified FALSH Address to operate

SysAddr16 (sysbase, offset) first defines a pointer to a 16-bit Half-word, with the address of the pointer sysbase and then an offset operation based on offset.  Since the address of the Half-word pointer is 2 byte aligned, each offset manipulation causes the address to be added 2. The Ultimate, SysAddr16 (sysbase, offset) is equivalent to defining a half-word pointer with the ultimate address (sysbase + 2offset). When using SysAddr16, set the Sysbase to the start address of FLASH , offset can be interpreted as the Half-word offset or offset address relative to the Flash start address. Assume that the starting address for Flash is 0x10000000,sysaddr16 (0x10000000, 0) points to the No. 0 h of 16-bit Flash Alf-word, SysAddr16 (0x10000000, 1 points to the 1th Half-word of 16-bit Flash. If you want to write 0xABCD to the No. 0 and 1th Half-word of Flash, you can use the following code :

*sysaddr16 (0x10000000, 0x0) = 0xabcd;*sysaddr16 (0x10000000, 0x1) = 0xABCD;

Next, we separately from the ARM processor angle and flash angle to the specific analysis.

From ARM's point of view:

Assuming that the start address of Flash is 0x10000000, because the ARM processor knows that the address space of the Flash is 0x10000000 ~ (0x10000000 +flash Capacity – 1), when the address space is accessed, the flash slices are set. Select the signal and output the low address to the address signal. Take *sysaddr16 (0x10000000, 0x1) = 0xABCD as an example. From the ARM processor point of view, The manipulation is to write 0xABCD to the address 0x10000002. So the ARM processor will end up in its address signal an-a0 output address 0x2, and output 0xABCD on d15-d0.

From the FLASH point of view:

Or take *sysaddr16 (0x10000000, 0x1) = 0xABCD For example, flash see the address is how much? Then analyze. When the ARM processor performs the operation, it will set up the corresponding flash chip select Enable signal and output 0x2 on the arm's address signal an-a0. Because the connection of the address signal of ARM and 16-bit Flash is staggered, so, Flash ultimate in its own address an-a0 see the signal is 0x1, equivalent to the ARM processor output address to the right to do a shift manipulation, exactly corresponds to the flash of the 1th Half-word. Meanwhile, Flash will see the data on its own d15-d0 0xABCD .

From the above analysis, we know that the value of offset specified in SysAddr16 is the value 16-bit Flash sees on its own address an-a0. So we can easily pass SysAddr16 (sysbase, offset) to flash into Line manipulation, where sysbase represents the flash start address, and offset represents the number of flash Half-word (Half-word offset or offset address)

Attention:

    1. In the description later in this section, Sysbase in SysAddr16 represents the start address of the flash, and offset in SysAddr16 represents the Half-word offset or offset address relative to the Flash start address. The value of OFFSET is also the value that 16-bit Flash sees on its own address signal an-a0;
    2. In sst39vf160 's command definition, all addresses are Half-word addresses for Flash, referring to the addresses seen on the Flash's own address signal an-a0.

Erase operation of the whole piece

A total of 6 cycles of bus write operations are required for the entire erase operation:

    1. Write 0X00AA to FLASH Half-word address 0x5555;
    2. Write 0x0055 to FLASH Half-word address 0x2aaa;
    3. Write 0x0080 to FLASH Half-word address 0x5555;
    4. Write 0X00AA to FLASH Half-word address 0x5555;
    5. Write 0x0055 to FLASH Half-word address 0x2aaa;
    6. Write the 0x0010 to the FLASH Half-word address 0x5555.

The corresponding code:

*sysaddr16 (sysbase, 0x5555) = 0X00AA;    Writes the value 0X00AA to the FLASH Half-word address 0x5555*sysaddr16 (sysbase, 0x2aaa) = 0x0055;    Writes the value 0x0055 to the FLASH Half-word address 0x2aaa*sysaddr16 (sysbase, 0x5555) = 0x0080;    Writes the value 0x0080 to the FLASH Half-word address 0x5555*sysaddr16 (sysbase, 0x5555) = 0X00AA;    Writes the value 0X00AA to the FLASH Half-word address 0x5555*sysaddr16 (sysbase, 0x2aaa) = 0x0055;    Writes the value 0x0055 to the FLASH Half-word address 0x2aaa*sysaddr16 (sysbase, 0x5555) = 0x0010;    Writes the value 0x0010 to the FLASH Half-word address 0x5555

Sector erase operation

A total of 6 cycles of bus writes are required for the sector erase operation:

    1. Write 0X00AA to FLASH Half-word address 0x5555;
    2. Write 0x0055 to FLASH Half-word address 0x2aaa;
    3. Write 0x0080 to FLASH Half-word address 0x5555;
    4. Write 0X00AA to FLASH Half-word address 0x5555;
    5. Write 0x0055 to FLASH Half-word address 0x2aaa;
    6. Write the 0x0030 to the Half-word address of the SECTOR that you want to erase.

The corresponding code:

*sysaddr16 (sysbase, 0x5555) = 0X00AA;    Writes the value 0X00AA to the FLASH Half-word address 0x5555*sysaddr16 (sysbase, 0x2aaa) = 0x0055;    Writes the value 0x0055 to the FLASH Half-word address 0x2aaa*sysaddr16 (sysbase, 0x5555) = 0x0080;    Writes the value 0x0080 to the FLASH Half-word address 0x5555*sysaddr16 (sysbase, 0x5555) = 0X00AA;    Writes the value 0X00AA to the FLASH Half-word address 0x5555*sysaddr16 (sysbase, 0x2aaa) = 0x0055;    Write the value 0x0055 to the FLASH Half-word address 0x2aaa*sysaddr16 (sysbase, addr >> 1) = 0x0030;    Writes the value 0x0030 to the Half-word address of the SECTOR to erase

Attention:

The 6th control period in the above code addr is a byte address from the ARM processor point of view, because at the time of erasure, the user would like to see the address from the arm angle, which is more convenient and more intuitive. In the SYSADDR16 macro definition, OFFSET Represents the Half-word offset relative to the flash start address, or the address that Flash sees on its own address signal an-a0. Therefore, a right-shift operation is required to convert the addr to a Half-word address.

For example, sst39vf160 the size of each SECTOR is 4k-byte. From the angle of the ARM and the user's point of view, the BYTE address of the SECTOR-0 relative to the Flash start address is 0x0; from Flash view SECTOR-0 The Half-word address is 0x0. From the angle of the ARM processor and the user's point of view, the Flash SECTOR-1 is relative to the flash start address of the byte address 0x1000; From Flash, SECTOR-1 's half-word address should be (0x1000 >> 1) = 0x800.

If you want to erase SECTOR-0, the 6th instruction of the above code should be:

*sysaddr16 (Sysbase, 0x0 >> 1) = 0x0030;

If you want to erase SECTOR-1, the 6th instruction of the above code should be:

*sysaddr16 (Sysbase, 0x1000 >> 1) = 0x0030;

Half-word Programming Operations

Write a Half-word data to flash, need 4 cycles of the bus write operation:

    1. Write 0X00AA to FLASH Half-word address 0x5555;
    2. Write 0x0055 to FLASH Half-word address 0x2aaa;
    3. Write 0x00a0 to FLASH Half-word address 0x5555;
    4. Writes the programming data (Half-word) to the corresponding Half-word address.

The corresponding code:

*sysaddr16 (sysbase, 0x5555) = 0X00AA;      Writes the value 0X00AA to the FLASH address 0x5555*sysaddr16 (sysbase, 0x2aaa) = 0x0055;      Writes the value 0x0055 to the FLASH address 0x2aaa*sysaddr16 (sysbase, 0x5555) = 0x00a0;      Writes the value 0x00a0 to the FLASH address 0x5555*sysaddr16 (sysbase, addr >> 1) = data;      Write the data to the corresponding Half-word address

Attention:

The addr in the 4th operation period in the preceding code is the byte address from the ARM processor's point of view, which is more convenient and more intuitive because the user would prefer to see the address from ARM's point of view when performing a write operation. And in SYSADDR16 's macro definition, Offset represents the Half-word offset relative to the flash start address. So you need to perform a right-shift manipulation to convert it to an Half-word address.

For example, to write data 0x0123 to address 0x0, corresponding to the No. 0 Hafl-word of FLASH, the corresponding Half-word address should be 0x0, the 4th instruction of the above code should be:

*sysaddr16 (Sysbase, 0x0 >> 1) = 0x0123;

If you want to write the data 0x4567 to address 0x2, corresponding to the 1th Half-word of Flash, the corresponding Half-word address should be 0x1, the 4th instruction of the above code should be:

*sysaddr16 (Sysbase, 0x2 >> 1) = 0x4567;

If you want to write the data 0x89ab to address 0x4, corresponding to the 2nd Half-word of Flash, the corresponding Half-word address should be 0x2, the above code of the 4th Directive should be:

*sysaddr16 (Sysbase, 0x4 >> 1) = 0x89ab;

Also if you want to write data 0xCDEF to address 0x6, corresponding to the 3rd Half-word of FLASH, the corresponding Half-word address should be 0x3, the above code of the 4th Directive should be:

*sysaddr16 (Sysbase, 0x6 >> 1) = 0xCDEF;
2.6 Concluding remarks

The above is a brief introduction to nor flash principle, and how to operate on nor flash, but does not include state query, protection and other manipulations. For more complex multi-chip flash parallel case is not discussed, if necessary, can be analyzed by themselves.

NOR Flash Erase and Principle analysis (i)

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