[Note] 5502 DSP reset Sequence)

For more information about datasheet translation, see datasheet 3.9.6.

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3.9.6 reset Sequence

When the reset # signal is low, the clock generator enters the bypass mode. At this time, the input clock is set to clkin or x2/clkin Based on the gpio4 status. When the level of the reset # pin changes from low to high, the following events are performed in sequence.

• Gpio6 and gpio7 are sampled at the rising edge of the reset signal. The status of gpio6 and gpio7 determines the 5502 reuse pin function (for details, see section 5502 datasheet 3.3, which provides configurable external ports and signals ). The statuses of gpio6 and gpio7 on the rising edge of the reset determine the external bus control register (xbsr) in parallel/host port MUX mode bit and Serial Port 2 MUX mode bit.
• Gpio4 is sampled at the rising time of the reset signal, and its status is used to set the clkmd0 bit of the always mode control register (clkmd, this bit is used to determine the DSP clock source. For the clkmd0 bit, either the internal oscillator output (internal oscillator output, oscout) or the x2/clkin pin is the input clock source of the DSP. If gpio4 is low during reset, clkmd0 is set to 0, and the internal oscillator and the external crystal generate an input clock for the DSP. If gpio4 is high during reset, the 0-bit clkmd0 is set to 1, and the input clock is provided directly by the x2/clkin pin.
• When the reset signal changes from low to high, the DSP will not immediately end from the reset status. In fact, an internal counter (internal counter) will count 41032 clock cycles to make the internal oscillator stable (only in the gpio4 bit low-level State ). In addition, the internal counter will add 70 reference clock cycles to transmit the reset signal to different parts of the device.
• After all the internal delay periods are completed, the bootm [] pins will be sampled and their values will be stored in the boot mode register (bootm_mode. The value in the bootm_mode register is used by bootloader to determine the Boot Mode of the DSP.
• ProgramThe stream starts after all internal delay periods.

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3.9.6 reset Sequence
When reset is low, the clock generator is in Bypass mode with the input clock set to clkin or x2/clkin,
Dependent upon the state of gpio4. after the reset pin transitions from low to high, the following events
Will occur in the order listed below.
• Gpio6 and gpio7 are sampled on the rising edge of the reset signal. The state of gpio6 and gpio7
Determines the function of the multiplexed pins of the 5502, see section 3.3, retriable external ports
And signals, for more information on Pin multiplexing. The state of gpio6 and gpio7 during the Rising
Edge of Reset determines the values for the parallel/host port MUX mode and the serial port 2 MUX Mode
BITs, respectively, of the external bus control register (xbsr ).
• Gpio4 is sampled on the rising edge of the reset signal to set the state of the clkmd0 bit of the clock
Mode Control Register (clkmd), which in turns, determines the clock source for the DSP. The clkmd0
Bit selects either the internal oscillator output (oscout) or the x2/clkin pin as the input clock source
For the DSP. If gpio4 is low at reset, The clkmd0 bit will be set to 0 and the internal oscillator and
External crystal generate the input clock for the DSP. If gpio4 is high, the clkmd0 bit will be set to 1 and
The input clock will be taken directly from the x2/clkin pin.
• After the reset signal transitions from low to high, the DSP will not be taken out of Reset immediately.
Instead, an internal counter will count 41032 clock cycles to allow the internal oscillator to stabilize (only
If gpio4 was low). The internal counter will also add 70 reference clock cycles to allow the reset signal
To propagate through different parts of the device.
• After all internal delay cycles have expired, the bootm [2: 0] pins will be sampled and their values will be
Stored in the boot mode register (bootm_mode). The value in the bootm_mode register will be used
By the bootloader to determine the Boot Mode of the DSP.
• Program flow will commence after all internal delay cycles have expired.