Notes for the user manual

The cc253x SOC sequence consists of multiple devices, primarily peripheral devices and memory sizes. The Flash size is 32 KB, 64 KB, kb, and kb respectively, but the SRAM size is 8 KB. The entire architecture of the cc2530xx SOC series can be divided into three parts: CPU and storage; peripherals, clock and power management; RF related modules. The storage medium is the core of the entire system because it connects the CPU and DMA controller and accesses the physical memory and peripheral devices through the SFR Bus. Four memory access points can be mapped to three physical memory types; 8 kb SRAM, Flash, and xreg/SFr registers. The device has many different peripheral devices: Debug interface, I/O controller, DMA controller, Timer 1, Timer 2, Timer 3, Timer 4, Sleep timer, ADC, random number generator, AES coprocessor, watchdog timer, serial port 0 and 1, full speed controller ).

The memory in the 8051cpu architecture has four different storage spaces. Its program storage and data storage have independent storage spaces.
Code: a read-only space for program storage, which has a 64 kB address
Data: a data storage space that allows the CPU to directly or indirectly read and write data through a periodic command. This space is only 256b. A space of B can be accessed directly or indirectly, while a space of B can only be accessed indirectly.

Xdata: A read/write space that requires 4-5 instruction cycles. This space has a 64kb address. Xdata access speed is lower than data access speed because code and xdata share a storage bus with a CPU core and the code prefetch command cannot be executed in parallel with xdata.

SFr: a storage space that can be read and written through a single instruction period. The storage space is B. The address of this SFr register is a multiple of 8, and each bit can be individually addressable.
These four different buckets are evident in the 8051 architecture, but some of them overlap in the device to simplify DMA transmission and hardware debugging. How different buckets map to three physical storages (flash, SRAM, and storage ing registers) will be described later.

Storage ing
The storage ing of the 8051 standard differs in two important aspects. First, some SFR and data buckets are mapped to the xdata bucket to run the DMA controller to access all the physical memory and perform DMA transmission between different 8051 buckets. Furthermore, you can select a ing scheme with two code buckets. The first scheme is that after the device is reset, only the program memory flash is mapped to the Code bucket, and the standard 8051 ing scheme. The second solution applies to code execution from SRAM. In this mode, the SRAM is mapped to 0x8000 ~ (0x8000 + SRAM_SIZE-1) in space. This ing Scheme 1 is shown.

Figure 1. Code storage ing

The top 32 KB of xdata is the read-only area, called xbank. Any 32 KB flash bank can be mapped to this point. This allows the software to access the entire flash memory. This area is usually used to store additional constant data.

 

The CPU has 18 interrupt sources, each of which has its own request flag in the interrupt mark SFr register. Each interruption source can be independently enabled and disabled, and the interruption has different priorities.

Each interrupt source can enable or disable the ien0, ien1, and ien2. To enable any interruption, take the following steps:
1. Clear the interrupt mark
2. Set the respective interrupt enable bits in the peripheral SFr register.
3. Set the respective interrupt enable bits in the ien0/ien1 or ien2 registers.
4. Set Global interrupt enable EA in register ien0
5. Interrupt the service program in the interrupt vector.

Interruption Overview

Interrupt Number Description interrupt name interrupt vector interrupt shielding (CPU) interrupt mark

0 RF txfifo and rxfifo overflow rferr 03 h ien0.rferrie tcon. rferrif

1. ADC 0bh ien0.adcie tcon. adcif

2 serial port 0 receive end urx0 13 H ien0.urx0ie tcon. urx0if

3 Serial Port 1 receives and ends urx1 1bh ien0.urx1ie tcon. urx1if

4 AES encryption and decryption ends ENC 23 h ien0.encie s0con. encif

5 Sleep Timer comparison st 2bh ien0.stie Ircon. STIF

6 Port 2 input/USB p2int 33 H ien2.p2ie ircon2.p2if

7. send and receive utx0 3bh ien2.utx0ie ircon2.utx0if through serial port

8 DMA transfer ends DMA 43 H ien1.dmaie Ircon. dmaif

9 timer 1 (16-bit) capture/compare/overflow T1 4bh ien1.t1ie Ircon. t1if

10 Timer 2 T2 53 H ien1.t2ie Ircon. t2if

11 timer 3 (8-bit) Comparison/overflow T3 5bh ien1.t3ie Ircon. t3if

12 timer 4 (8-bit) Comparison/overflow T4 63 h ien1.t4ie Ircon. t4if

13 Port 0 input p0int 6bh ien1.p0ie Ircon. p0if

14 Serial 1 transmission end utx1 73 h ien2.utx1ie ircon2.utx1if

15 Port 1 input p1int 7bh ien2.p1ie ircon2.p1if

16 RF General interrupt RF 83 H ien2.rfie s1con. rfif

17 Timer mode: wdt 8bh ien2.wdtie ircon2.wdtif Overflow

The fastest response time to an interruption is 7 machine cycles. One is used to detect the interruption and the other is used to execute the lcall command. An interrupt is divided into six interrupt priority groups. The priority of each group is set through ip0 and IP1. Each group has four levels of priority. If an interruption with the same priority occurs at the same time, the query order is used to determine the priority request.

CPU registers
Two data pointers, dptr0 and dptr1, are used to accelerate reading or writing data to memory and to access code or xdata space. Use the DPS Data Pointer to select the Data Pointer used for instruction execution in the register.

Register R0-R7.
A register bank with four groups of 8 registers is mapped to the data storage space. The addresses are 0x00-0x07, 0x08-0x0f, 0x10-0x17, and 0x18-0x1f. Each bank contains eight octal register R0-R7. Set the register bank through psw. RS [1:0. Internally, bank0 uses triggers to store data, while 1-3 uses SRAM to store data, which can save energy. The use of bank0 can save about 200ua of current than the use of bank1-3.

Stack pointer
The stack in the data storage space increases upwards. The push command First adds the SP and then copies the byte into the stack. After the reset, the SP is initialized to 0x07, And the stack is stored starting from 0x08. Because 0x08 is the R0 of the Second Bank, if the program requires multiple register banks, the default sp value must be modified.

Storage Medium
The storage arbitration server resolves conflicts between the CPU and DMA access to all physical memory except the internal registers of the CPU. When there is a conflict between the CPU and DMA, the storage medium selects one as the main controller of the bus to resolve the conflict. The control registers memctr and fmap are used to control various aspects of the storage subsystem. Memctr. xmap must be enabled when executing a program from Ram. Flash bank ing register fmap controls the ing of 32 KB physical code bank to the program address area 0x8000-0xffff. Xmap: xdata ing to code when this is set, the SRAM xdata region maps from 0x0000 to SRAM_SIZE-1) to the code region, that is, 0x8000 to 0x80000 + SRAM_SIZE-1. this enables code execution from Ram. Xbank: xdata
Select a bank to control the ing of those physical flash storage banks to the xdata area. When the value is set to 0, the root bank is mapped.