[Original black gold tutorial] [FPGA-driver I] experiment 12: Serial Port module ①-send

Tutorial 12: Serial Port module ①-send

The serial port is a typical experiment, and many of you may have done a bad job, but I will introduce it as an example. We know that the serial port can be sent and received. The objective of the experiment 12 is to achieve serial transmission, but the difference is that... I will use another idea to implement serial transmission.

Figure 12.1 PS/2 sending sequence and serial sending Sequence.

As shown in Figure 12.1, the serial sending sequence is like a bird with a broken wings, and the whole transmission protocol is controlled without a clock signal. In addition, the serial port sending sequence is similar to the PS/2 sending sequence... by default, a frame of PS/2 data has 11 bits, and the serial data of this frame also has 11 bits. The bit allocation is shown in Table 12.1:

Table 12.1 Bit Allocation of One-frame serial port data.

Bit Allocation	Bit Definition
[0]	Start position
[8:1]	Data bit
[9]	Check bit
[10]	Stop bit

As shown in Table 12.1, [0] indicates the starting position for low pulling, [8] indicates any filled data bit, [9] indicates any filled check bit, and [10] indicates the stop position for high pulling.

Figure 12.2 FPGA sends a frame of serial data (regardless of the baud rate ).

Suppose we ignore the baud rate and Use FPGA to send a frame of serial data... as shown in 12.2, a frame of 11-bit serial port data is sent out using a total of 11 rising edges. Therefore, you can use the following command to describe the result in Code 12.1:

      reg [10:0]D1;

     always @（posedge CLOCK）

         case（i）

            0,1,2,3,4,5,6,7,8,9,10:      

            begin TXD <= D1[i]; i <= i + 1‘b1; end

            ......

         endcase

Code 12.1:

As shown in Code 12.1, register D is an 11-bit wide register and drives the txd output port ~ 11 According to the I-bit addressing, the D1 content is sent one by one.

Although the serial transmission protocol is very similar to the PS/2 transmission protocol, the serial transmission protocol is also different. The serial transmission protocol has the baud rate concept, and the serial port Protocol has a variety of baud rates. Common baud rates include 9600 bps or 115200 BPS, and the lowest baud rate is 110 bps, the maximum value is 256000 BPS (currently tentative ). The so-called baud rate is how many bits of data can be sent by the serial port within one second. In addition, the baud rate is also the cycle of one bit of data, or the retention time of one bit of data. Take 115200 BPS as an example:

1/115200 = 8.68e-6

The one-bit data cycle of the 115200 baud rate is 8.68us. If we use a clock frequency of 50 MHz to quantify it:

(1/115200)/(1/50e + 6) = 8.68e-6/20e-9

= 434

Figure 12.3 FPGA sends a frame of serial data (considering the baud rate ).

If Figure 12.3 considers the baud rate of 115200, The result 12.3 shows that each bit of data maintains 434 clocks.

For this purpose, it can be expressed as follows, as shown in code 12.2:

      reg [10:0]D1;

      reg [8:0]C1;

     always @（posedge CLOCK）

         case（i）

            0,1,2,3,4,5,6,7,8,9,10:    

             if( C1 == 9’d434 -1 ) begin C1 <= 9’d0; i <= i + 1’b1; end  

            else begin TXD <= D1[i]; C1 <= C1 + 1‘b1; end

            ......

         endcase

Code 12.1:

As shown in Code 12.1, STEP 0 ~ 10. A clock is no longer maintained, and 434 clock is maintained for each step. Therefore, the data sent for each txd is also kept at 8.68us.

In addition, the serial transmission protocol can not only customize the baud rate, but also the Bit Width of a frame of data. The custom content is shown in Table 12.2:

Table 12.2 customizes a frame of data.

Custom Data bit	Custom content
Data bit	5 ~ 9
Check bit	Yes/No
Stop bit	1 ~ 2

As shown in Table 12.2, data that can be customized contains data bits. The default value is 1 byte, And the custom content is 5-byte ~ 9 bits, check bits can also be set to either or none (by default), and the Stop bits can also be increased to 2 bits (by default, 1 bits ). In any case, Table 12.2 is a relatively official custom content. As long as the reader is happy, any malformed custom content may also be implemented.

After understanding, we can start modeling.

Figure 12.4 modeling diagram of experiment 12.

Figure 12.4 is the modeling diagram of experiment 12, but the content is cool... the tx_demo of the combination module contains a core operation and a TX function module. Core operations are responsible for calling the Tx function module, that is, controlling communication signals and data input. After the Tx function module is enabled, idata is sent through the txd output end.

After the operation is completed, the feedback indicates that the one-time operation has been completed.

Tx_funcmod.v

Figure 12.5 modeling of the Tx function module.

As shown in 12.5, the left side of the module has a Q & A signal and 8-bit idata. The right side is the top layer txd signal. In addition, the baud rate of one frame of data is 115200 bps.

1.    module tx_funcmod

2.    (

3.         input CLOCK, RESET,

4.         output TXD,

5.         input iCall,

6.         output oDone,

7.         input [7:0]iData

8.    );

9.         parameter B115K2 = 9‘d434; // formula : ( 1/115200 )/( 1/50E+6 )     

The above content is related to the inbound and outbound declarations, and the 9th rows are constant declarations with a baud rate of 115200.

11.         reg [3:0]i;

12.         reg [8:0]C1;

13.         reg [10:0]D1;

14.         reg rTXD;

15.         reg isDone;

16.         

17.         always @( posedge CLOCK or negedge RESET )

18.             if( !RESET )

19.                  begin

20.                         i <= 4‘d0;

21.                         C1 <= 9‘d0;

22.                         D1 <= 11‘d0;

23.                         rTXD <= 1‘b1; 

24.                         isDone <= 1‘b0;

25.                  end

The above content is related to the Register declaration and reset operation.

26.              else if( iCall )

27.                  case( i )

28.                    

29.                         0:

30.                         begin D1 <= { 2‘b11 , iData , 1‘b0 }; i <= i + 1‘b1; end

31.                         

32.                         1,2,3,4,5,6,7,8,9,10,11:      

33.                         if( C1 == B115K2 -1 ) begin C1 <= 8‘d0; i <= i + 1‘b1; end

34.                         else begin rTXD <= D1[i - 1]; C1 <= C1 + 1‘b1; end

35.    

36.                         12:

37.                         begin isDone <= 1‘b1; i <= i + 1‘b1; end

38.                         

39.                         13:

40.                         begin isDone <= 1‘b0; i <= 4‘d0; end

41.                    

42.                    endcase

43.                        

The above content is part of the core operation. If (iCall) in the first row indicates that the module does not work if it is not enabled. Step 0 is used to prepare the data to be sent. Here, 2 'b11 is the stop bit and check bit (left blank), and 1 'b0 is the start bit. Step 1 ~ 11 is used to send a frame of data. Step 12 ~ 13 is used to feedback the completion signal and return the step.

44.        assign TXD = rTXD;

45.        assign oDone = isDone;           

46.    

47.    endmodule

The above content is the declaration of the driver output.

Tx_demo.v

The connection deployment is more specific to the code.

1.    module tx_demo

2.    (

3.         input CLOCK, RESET,

4.         output TXD

5.    );

6.        wire DoneU1;

The above content is related to the inbound and outbound declarations.

8.        tx_funcmod U1

9.         (

10.              .CLOCK( CLOCK ),

11.              .RESET( RESET ),

12.              .TXD( TXD ),

13.              .iCall( isTX ),

14.              .oDone( DoneU1 ),

15.             .iData( D1 )

16.         );

The above content is the instantiation of the Tx function module, where iscall is driven by istx, and idata is driven by D.

18.         reg [3:0]i;

19.         reg [7:0]D1;

20.         reg isTX;

21.         

22.         always @ ( posedge CLOCK or negedge RESET )

23.             if( !RESET )

24.                  begin

25.                         i <= 4‘d0;

26.                         D1 <= 8‘d0;

27.                         isTX <= 1‘b0;

28.                    end

The above is a register declaration, 23rd ~ The 28 rows are the reset operations of these registers.

29.              else

30.                  case( i )

31.                    

32.                        0:

33.                         if( DoneU1 ) begin isTX <= 1‘b0; i <= i + 1‘b1; end

34.                         else begin isTX <= 1‘b1; D1 <= 8‘hA1; end

35.                         

36.                         1:

37.                         if( DoneU1 ) begin isTX <= 1‘b0; i <= i + 1‘b1; end

38.                         else begin isTX <= 1‘b1; D1 <= 8‘hA2; end

39.                         

40.                         2:

41.                         if( DoneU1 ) begin isTX <= 1‘b0; i <= i + 1‘b1; end

42.                         else begin isTX <= 1‘b1; D1 <= 8‘hA3; end

43.                         

44.                         3: // Stop

45.                         i <= i;

46.                    

47.                    endcase

48.    

49.    endmodule

The above content is the core operation content, STEP 0 sends data 8'ha1, step 1 sends data 8' ha2, step 2 sends data 8' Ha3.

After compilation, download the program and connect the program to the computer and the Development Board. Open the serial port debugging assistant, set the baud rate to 115200, the data bit to 8, the check bit is casual, the stop bit is 1 bit... after the event, the display mode is set to hex (hexadecimal ). After the program is downloaded, the serial port debugging assistant displays A1, A2, and A3.

Details 1: complete individual module

The TX function module of experiment 12 is already a complete individual and can be called directly.

[Original black gold tutorial] [FPGA-driver I] experiment 12: Serial Port module ①-send