(Original) how to build a system that can run μC/DE2-70 on the OS-II with the system? (SOC) (nano II) (μC/OS-II) (DE2-70)

Abstract
In this paper, the use of Quartus II, system builder, niosii eds from 0 to create a can run on the DE2-70 μC/OS-II niosii system, beginners can use this example to familiarize themselves with the use of Quartus II, FPGA builder, and niosii eds, and to understand the development process of FPGA-based embedded systems.

Introduction
Use environment: Quartus II 8.1 + NiO II eds 8.1 + DE2-70 (Cyclone II ep2c70f896c6n)

These four labs were originally designed together, starting from 0, beginners are gradually familiar with Quartus II, systems builder, niosii eds, aveon bus slave, and aveon bus master.

(Original) how to build a system that can run μC/DE2-70 on the OS-II with the system? (SOC) (Quartus II)
(Original) how to design a seven-segment controller? (SOC) (Quartus II)
(Original) how to design an SD card WAV player? (SOC) (Quartus II)
(Original) how to design a digital photo frame? (SOC) (Quartus II)

(A lot of people should have been checking. Since the time was a little long, it was implemented on Quartus II 8.1 at that time, and does not guarantee that the database can be normally renewed in the future Quartus II version, if you encounter a problem with the niosii specification change or Quartus II timing, please renew it on your own)

Why do we need to establish a niosii system from scratch?

1. You can optimize the system by yourself.

2. Many samples use the hardware-based OpenGL code. You need to build the niosii system from scratch. You cannot use the niosii system established by Altera or Youjing technology.

3. DE2-70 is not the development of the original release of Altera, but the edition of Youjing technology ODM, many weeks are different from the original version of Altera, therefore, many examples of Altera's hand-held networks cannot be used, and they must have their own ability to build a system from the hardware to the operating system, later, there will be a method to transplant the original examples of Altera region to the DE2-70 and perform optimization.

DE2-70 Development

 

DE2-70 System Architecture

This example shows the system architecture
The final result is that you want to have more dynamic rows in the μC/OS-II, And the ledg [] can be controlled by Sw.

Quartus II
Use Quartus II to create a new project

Step 1:
Create a new project

Step 2:
Introduction

Press next second.

Step 3:
Enter the project path, project name, and top Module name.

Press next second.

Step 4:
C:/DE2-70/hello_ucoⅱ object category has not been set up, whether this object category is set up

Press Yes (y) then.

Step 5:
Add existing project to project,

Since we have not yet established any issue cases, we should press Next iteration.

Step 6:
Select FPGA Compaction

FPGA used by DE2-70 isCyclone II ep2c70f896c6nAccording to the naming rules of Altera for FPGA:
Ep2c: Cyclone II
70: 70 families
F: fbga
896: 896 pin
C6: speed grade 6

Press next second.

Step 7:
Select 3rd party's EDA tool

Quartus II supports 3rd part EDA tools, such as ModelSim. If it is useful, you can set it here. If it is not used currently, press Next iteration later.

Step 8:
The last Summary

Press finish.

 

Part 1
Build a brand-new system of niosii with the help of the system.

Step 9:
Dynamic and Dynamic System File System Builder

Step 10:
Enter the system name and select "cmdname ".

If you select the IP address that you set later in the system, the system uses the IP address that the system uses. If you are familiar with the VHDL, you can use the optional VHDL. This setting does not limit that you will be able to use only the following code in the future, that is to say, you can use the entity of the VHDL module, the entity of the VHDL module, and the module of the Tilde can always be used.

Note that the upper left corner of the device family is Cyclone II, and the upper right corner of clk_0 is 50.0 MHz, although the nio ii can only run 50.0 MHz in the DE2-70, but this is because the CPU downgrading is running, under normal circumstances, the Nios II can run 100.0 MHz in the DE2-70, So we then intend to use the PLL to convert the CLK times to 100.0 MHz.

Step 11:
Add PLL

Generate the CLK required by the CPU and sdram of the niosii. On the left side, press the mouse and the left side to add the PLL to the system.

Page1

Simply accept the parameter value and press Next iteration.

Page2

Simply accept the parameter value and press Next iteration.

Page3

Simply accept the parameter value and press Next iteration.

Page4

Set the 100 MHz CLK required by the CPU and set the clock multiplication factor to 2. Note that the actual settings output 100.000000 MHz.

When using altpll to generate CLK, note that not any CLK can be produced. If atlpll can synthesize CLK, it will appear aboveAble to implement the requested PLL.

Press next second.

Page5

Set the 100 MHz CLK required for the SDRAM, but a-65 degree phase shift is required.

Press next second.

 Page 6

If you do not need other clks, press Next second instead.

Page 7

Simply accept the parameter value and press Next iteration.

Page 8

Simply accept the reset value and press finish.

Finally, press finish.

In the end, pll_0: pll_0.s1 must be connected to an avron-mm master's failover messages will appear, because pll_0 is a server Load balancer IP address, it must be controlled by the master IP address. Wait a moment later until the system is added to the master IP address (the system is the niosii CPU.

Step 12:
Change the CLK name

Change CLK to a meaningful name.

Change clk_0 to clk_50.
Replace pll_0_c0 with cpu_clk.
Replace pll_0_c1 with sdram_clk.
Pll_0 is changed to PLL.

Step 13:
Add the niosii CPU

For the root worker, you need to select the following:
1. niosii/E (economy): the minimum number of Le occupied, the minimum number of functions, and the slowest speed.
2. niosii/s (standard): The speed is balanced with the Le, and has the general functions of the niosii CPU.
3. niosii/F (full): the largest number of Le-consuming resources, the largest number of functions, and the fastest speed.

In this example, you can choose to use niosii/F.

You do not need to set the Reset vector and the exception vector when setting the values, because the Host IP Address has not been updated yet.

For other settings, you only need to accept the specified values. Press finish.

Change cpu_0 to CPU.

Due to the addition of the niosii CPU, the niosii CPU is a typical master IP address. The system automatically associates the CPU (master) with the PLL (slave), so pll_0: pll_0.s1 must be connected to an avron-mm master without warning.

The newly added warning is the Reset vector and exception vector mentioned by the handler, and is finally set.

Step 14:
Add on-chip memory

A small number of m4k memory in FPGA, is the fastest in all the memory of the DE2-70, but the smallest memory.

Set 30 Kbytes on-chip memory.

The total memory size is related to the available m4k memory volume. The size of memory on-chip memory varies depending on the FPGA-type CPU core, and the use of megafunction (such as fcfifo.

Change onchip_memory2_0 to onchip_mem.

It is normal that the two cannot be at 0x1000 messages are sent normally, because the source address 0 x of onchip_mem is not valid in the system. After all IP addresses are added, in the end, the slave IP address will be reset once again.

Step 15:
Tristate bridge added to ssram

Because the databus of ssram and Flash are tristate, the tristate bridge must be used for interconnection between the nano ii cpu and ssram and flash.

Simply accept the reset value and press finish.

Change tri_state_bridge_0 to tristate_bridge_ssram.

NowTristate_bridge_ssram: tristate_bridge_ssram.tristate_masterMust connected to avron-mm tristate slave's failover messages, because the master interface of tristate_bridge_ssram must be associated with the slave IP address. After the ssram controller is added, you can solve this problem.

Step 16:
Add ssram

 

Simply accept the reset value and press finish.

Change ssram_0 to ssram.

Associate ssram with tristate_bridge_ssram.Tristate_bridge_ssram: tristate_bridge_ssram.tristate_masterMust connected to aveon-mm tristate slave failed messages.

Ssram is a memory of the On-chip memory on the DE2-70, and its capacity increases from kb to 2 MB. Most of the runtime instances in ssram are fully compatible.

Step 17:
Add tristate bridge to flash

Just as step 15 adds a tristate bridge and changes the name of the bridge to tristate_bridge_flash

Step 18:
Add flash

In attribute, set address width to 22 and data width to 16.

In timing, set wait to 100. Press finish.

Change cfi_flash_0 to cfi_flash.

Compare cfi_flash with tristate_bridge_flash.Tristate_bridge_flash: tristate_bridge_flash.tristate_masterMust connected to aveon-mm tristate slave failed messages.

MoreCPU. instruction_master: onchip_mem.s1(0x1000 .. 0x8fff) overlapsCfi_flash.s1(0x0 .. 0x7fffff) andCPU. data_master: onchip_mem.s1(0x1000 .. 0x8fff) overlapsCfi_flash.s1(0x0 .. 0x7fffff) two parameter values, because the source cfi_flash address of the system is 0x00000000 .. 0x007fffff has been 0x00001000 with onchip_mem .. 0x000087ff indicates a redundant phase. After all the controllers are added, the final IP address of all controllers will be reset.

Flash is the only record of information stored after the computer on the DE2-70. If you want the niosii program to record the computer, you can record it through one phone, we need to place the runtime on flash.

Step 19:
Add SDRAM

In Memory profile, Set
Presets: custom
Data width: 32
Chip select: 1
BANKS: 4
Row: 13

Note that the last memory size is 64 Mbytes.

In timing, Set
Issue One refresh command every: 7.8125 us
Delay after powerup, before initialization: 200 US

Change sdram_0 to SDRAM.

In this case, the Response Message of the SDRAM base address will be displayed, and a final solution will be made.

Step 20:
Add JTAG UART

Jtag uart is a method for generating serial numbers in the PC-to-the-machine sequence and the serial/serial input parameter of the niosii standard. For example, if printf () passes through the jtag uart, after the USB blster, the console shown in the result on the PC's nioii eds, scanf () after USB blster passes through the jtag uart, the hacker is added to the system's niosii.

Simply accept the reset value and press finish.

Change jtag_uart_0 to jtag_uart.

Step 21:
Add UART (RS-232 serial port)

UART is another method for generating serial numbers in the PC-to-the-machine sequence and the serial/serial input parameter of the niosii standard. For example, printf () can also pass through UART. After RS232, the console that shows the result is displayed on the PC's nioii eds, scanf () it can also be passed through RS232 through UART to upload the program to the system's niosii.

Tick include CTS/RTS pins and control register bits. If you want to accept other settings, press finish.

Change uart_0 to UART.

Step 22:
Add Timer

In this case, we need to add two timers, one being system clock and the other being timestamp.In particular, μ c/OS-II must be timestamp timer, otherwise there is no way to merge rows.

Simply accept the reset value and press finish.

Change timer_0 to sys_clk_timer.

Add timestamp_timer to the step worker with the same weight.

Step 23:
Add System ID

The System ID is used by the system builder to provide an identifier for each system. The niosii eds prevents users from copying *. Sof that does not comply with *. PTF.

Simply accept the reset value and press finish.

Change sysid_0 to sysid.

(Make sure to change the name of "sysid" to "sysid", because the system uses sysid to determine whether to generate a sysid .)

Step 24:
Add character LCD

For the 16x2 character LCD ON THE DE2-70, can be used as the standard output specification of the nano II. For example, printf () can also display strings on the LCD through the character LCD.

Simply accept the reset value and press finish.

Change LCD _0 to LCD.

Step 25:
Add LED Pio

Add two led PIO, one for ledg and the other for ledr.

Ledg

Because ledg [8: 0] is used for export, width is set to 9 and output ports only is selected. Press finish.

Change pio_0 to pio_ledg.

Ledr

Add ledr Pio as you add ledg Pio.

Because ledr [] and projection is used for output, width is set to 9 and output ports only is selected. Press finish.

Change pio_0 to pio_ledr.

Step 26:
Add input Pio

Add two input PIO, one as the key and the other as the SW.

Key

 

Select partition Pio (parallel I/O) as in step 25 ).

Because key [3: 0] is used in batch input, width is set to 4 and input ports only is selected. Press finish.

Change pio_0 to pio_key.

SW

Because SW [] is used in batch input, width is set to 18, and input ports only is selected. Press finish.

Change pio_0 to pio_sw.

Step 27:
Reset base address

In the past, many errors and warnings were caused by the Controller's base address re-encryption. Currently, All controllers used have been added to the FPGA builder to allow the system builder to reset the base address.

Even the messages are lost.

Step 28:
Set the Reset vector and exception vector of the niosii CPU

In step 13, when I set the NIO II CPU, the Reset vector and exception vector were not set because no memory was attached at the time, now set the response.

Simply put, when the Reset vector is the system reset, the CPU will jump to the address specified by the Reset vector to limit the line,Therefore, the recorder specified by the Reset vector must be a non-intrusive reporter., In the DE2-70 only Flash.

When the exception vector generates a hardware interrupt or software exception, the CPU will jump to the address specified by the exception vector to make it more efficient,We will direct the exception vector to the fastest runner., Usually on-chip memory or ssram.

Finally, press finish.

 

Finally, complete the configuration of all the Enis. Note that there are only three messages below. The first two warnings indicate that pio_key and pio_sw need to input testmessages, which can be ignored.

Step 29:
Product-based systems

Press generate to generate nios_ii.ptf. This requires a period of time, depending on the CPU running speed.

Press save to save nios_ii.system. This file records all the controllers and settings of the system builder.

After about 1 minute and a half, the system successfully generate the system.

You can generate the system with the help of the system.
1. nios_ii.ptf generation:
This case will be based on the Systems library generated by the niosii eds, which can be accessed by the niosii compiler and the μC/OS-II.

2. generate the following node for each controller:
Based on the FPGA technology, the system must be produced by Quartus II *. sof implements compaction into FPGA, and the FPGA builder will generate the FPGA code of controller for Quartus II. You can find that the root project of the project has a lot more *. V, which is generated by the systems of the system builder.

 

Top Module
The system builder generates modules for each controller, and requires a top module that matches the I/O port of the DE2-70.

Step 30:
Create top mudule

Create a hardware mesh repository in c: \ DE2-70 \ hello_ucoⅱ.
Labelpolicfiles.zip, where hello_ucosii.v is an unfinished top module, put hello_ucosii.v and reset_delay.v under c: \ DE2-70 \ hello_ucoⅱ \ contents.

Four locations must be modified before the top module can be completed.

256 rows

  . Sdram_clk (),//SDRAM clock//To do !! SDRAM clock output
 

Change

 
  . Sdram_clk (sdram_clk ),//SDRAM clock
 

217 rows

  //To do !! Assign sdram clk to odram0_clk
 

Change

 
  AssignOdram0_clk=Sdram_clk;//Sdram0 clock
 

229 rows

  //To do !! Assign sdram clk to odram1_clk
 

Change

 
  AssignOdram1_clk=Sdram_clk;//Sdram1 clock 
 

Because the DE2-70 has 2 Gbit/s SDRAM, so assign twice CLK.

277 rows

  . Zs_dq_to_and_from_the_sdram (),//SDRAM data bus 32 bits//To do !! SDRAM Data Bus output
 

Change

 
  . Zs_dq_to_and_from_the_sdram (dram_dq ),//SDRAM data bus 32 bits
 

Because dram_dq is an inout sequence, it cannot be connected by wire sequence. Instead, it must be directly merged to the inout port.

 

How do you know what ports are available in the system?

Enable nios_ii.v. This is the FPGA code generated by the system's system tool 『Module nios_ii (』, You can find the module definition of the system, the top module is the definition of the root module, which is to the DE2-70 I/O port.

Step 31:
Set reserved all unused pins as input tri-stated

Assignment-> Device

Device and pin options...

Unused pins: reserve all unused pins: As input tri-stated

This step must be done. Otherwise, there will be the following warning messages when the niosii cannot be completed. Beginners often ignore this step !!

Step 32:
Import pin assignment

The de2_70_pin_assignments.csv file in the labelled files.zip file records the bitwise of all I/O in the DE2-70.

Assignments-> Import assignments...

Export to de2_70_pin_assignments.csv, and press OK then.

View pin assignment result

Assignments-> Assignment Editor

The pin assignment settings are successful.

This step must also be done. Otherwise, the following warning messages will appear when the niosii cannot be completed. Beginners often ignore this step !!

Step 33:
Set nceo to use as regular I/O

Assignments-> Device

Device and pin options...

Dual-purpose pins

Change nceo to use as regular I/O

This is a problem of DE2-70 design, which does not need to be set in de2 or other Altera's development. If this parameter is not set, Quartus II will generate the following warning messages during the renewal and the loss will occur.

Step 34:
Quartus II

It takes 2 to 10 minutes, depending on the CPU speed.

 

Programmer part
Use programmer to import zookeeper *. Sof into FPGA

Step 35:
Dynamic programmer

Set USB-blaster according to hardware setup.

Select available USB-blaster

Start with "START" to import *. Sof into FPGA. When 100% is displayed, it indicates that the compaction operation is successful.

For the moment, the hard part ends, and the next part is the actual part.

 

Niosii EDS
Use the niosii eds to develop the niosii Compiler

Step 36:
Use Hello wrold to verify whether the hardware is successfully configured

Quartus II can be properly renewed, which does not mean that the hardware design is successful, the parameter settings of each controller in the System Builder are optimized, the CLK parameter settings are optimized, the top module is optimized, and the Quartus II parameter settings are optimized... and so on. Therefore, the most simple "Hello World" operator is used to initialize the hard body. If "Hello world" is used, no rows can be written, you don't need to worry about the hardware part. First, you can look back for the hardware part bug.

Right-click "Hello World template" and specify the system PFT file: C: \ DE2-70 \ hello_ucoⅱ \ nios_ii.ptf in the System Builder system. Finally, press finish.

Niosii eds will generate two projects based on the selected project template and the System File System of the system:
1. hello_world_0: niosii software project.
2. hello_world_0_syslib: niosii system library project. (System Library=Hal(Hardware prepare action layer) =BSP(Board support package) =Driver)

Select hello_world_0, right-click the mouse, and select system library Properties

Select sys_clk_timer for the system clock timer, and run the entire system clock timer on the SDRAM. You can also run the system on other memory instances because the sdram capacity is the largest and the clk of the sdram requires phase shift, therefore, the most common problem occurs in the case of SDRAM. Therefore, we recommend that you use SDRAM here, so that you can manually compile other memory instances.