OVL assertions (constantly updated)

Abstract:Describes statements of OVL assertions.

Introduction:This article is a note for reading "OpenGL Digital System Design-register transfer level Synthsis, testbench, and verification ".

Body:

1. Advantages of Assertion Verification:
1> convenientProgramTesting can improve the automation of testing compared with ordinary testbench.
2> added readability for verification.
3> approved by the formal verification tool.
4> Design Description and test process are included in a module.

2. General assertion format:
Assert_name
# (Static_parameters)
Instance_name
(Dynamic_arguments); // do not forget the semicolon. The following example saves

3. Some common statements:
1> assert_always
# (Severity_level, property_type, MSG, coverage_level)
Instance_name (CLK, reset_n, test_expr)
Always verify: test_expr, ensure it is on the specified clock edge (CLK indicates the rising edge ,~ CLK indicates the descent edge)
Is true. If not,
And displays MSG.
If reset_n is 1' B1, the assertion monitor is always active.
2> assert_change
# (Severity_level, width, num_cks, action_on_new_start,
Property_type, MSG, coverage_level)
Instance_name (CLK, reset_n, start_event, test_expr)
Verification: tset_expr changes within the given number of clocks (num_cks) after start_event.
Width indicates the Bit Width of test_expr, and num_cks indicates that test_exps changes after the num_cks clock period.
3> assert_one_hot
# (Severity_level, width, property_type, MSG, coverage_level)
Instance_name (CLK, reset_n, test_expr)
Verification: When the monitor is activated, only one of the N-bit test_expr is 1.
Width indicates the Bit Width of test_expr.
For example, auxiliary logic can be added to the design description for monitoring.
Reg [3: 0] old;
Always @ (posedge CLK) Old <= Q;
(Because it is a non-blocking value assignment, the old value is assigned to old in the next clock cycle, and Q is the new value)
Assert_one_hot # (1, 4, 0, "Err: Not Gray", 0)
Aoh (~ CLK ,~ RST, (old ^ q ));

4> assert_cycle_sequence
# (Severity_level, num_cks, necessary_condition,
Property_type, MSG, coverage_level)
Instance_name (CLK, reset_n, event_sequence)
Verification: The occurrence of a series of events at a given clock cycle.
Verification when necessary_condition is 0: in the specified sequence, if all the previous statuses
Arrival, whether the final status has arrived;
If the value is 1, verify that the status after the first status arrives.

5> assert_next
# (severity_level, num_cks, necessary_condition,
property_type, MSG, coverage_level)
instance_name (CLK, reset_n, start_event, test_expr)
verify whether test_expr occurs from the start to the specified clock period.
6> assert_implication
# (severity_level, property_type, MSG, coverage_level)
instance_name (CLK, reset_n, antecedent_expr, consequence_expr)
verify that the specified clock along antecedent_expr is correct. If yes, verify
consequence_expr is correct.

 7> assert_no_overflow
# (Severity_level, width, Min, Max,
Property_type, MSG, coverage_level)
Instance_name (CLK, reset_n, test_expr)
Verify that test_expr is in valid state (some status codes do not use all statuses)
Width indicates the Bit Width, Min, and Max of the variable to be tested (usually in the current State ).
And the minimum value.