Parsing of the SDRAM Controller

This blog post is not original. It organizes various online statements and integrates them to facilitate future queries. If any, please let us know.

 

1. What is the difference between precharge and refresh?

Plj: Both of them charge and write back the capacitor of the storage unit. However, the difference is:

Precharge operates on all active rows of (one or all banks) and is random. The addresses of the operated working rows are different in different banks.

Refresh operates on all rows in sequence and has a fixed cycle. The operated rows are the same in each bank.

2. What is the difference between autorefresh and selfrefresh?

Plj: autorefresh is the refresh command that the user sends to the chip according to the specified cycle.

Selfrefresh is the refresh command sent to itself by the internal logic of the chip.

No address is required for any refresh. It is an automatic operation in the chip.

3. What is the difference between R/W and auto precharge?

Plj: With autoprecharge: During R, the chip automatically generates the precharge command before the (CL-1) Clock (the last valid output data.

At W, the chip automatically generates the precharge command after (the last valid output data) (twr.

If autoprecharge is not included, the user must generate the precharge command at the preceding time.

4. The Cl parameter is only valid for read operations.

5. Only one row in each bank is active and R/W can be performed.

If you want to operate another row in the same bank, you must use precharge to close the current working row and then use the active destination row to R/W

6. Each bank has an active row and operates the row among banks in sequence. This avoids unnecessary clock cycles consumed by R/W and improves data transmission bandwidth.

 

 

 

1. precharge during normal read
Both auto_precharge and manual precharge are issued at the rising edge of the CL-1 before the last valid data (LVD)
2. Manually precharge ends read
The manual precharge emits a CL-1 of clock rising edges before the last valid data (LVD)
3. Manually terminate the read
Burst terminate CL-1 clock rising along before the last valid data (LVD)


4. precharge during normal write
Both auto_precharge and manual precharge are triggered at the rising edge of the twr/tdpl time after the last valid data (LVD ).
5. Manually precharge termination of write
Manual precharge emits the rising edge of the twr/TDP time after the last valid data (LVD)
Or enable dqm to block data written at the same time in precharge.
6. Manually terminate write
Burst terminate emits the first rising edge of the clock after the last valid data (LVD ).


7. What is the difference between burst terminate and manual precharge in ending read/write?
The BT and manual precharge commands are not allowed during the R/W process with autoprecharge.
Burst terminate is applicable to R/W on the entire page and sudden R/W without autoprecharge

 

 

 

1. The burst mode of SDRAM

SDRAM is a command-type action device. If only one read/write data is available, you must first run the command to use it. To increase work efficiency, a command is generated to send, the mode of writing multiple data. This is the burst mode.

Burst mode is a high-speed read/write mode that uses the internal column address generator. As long as you set the initial column address, the subsequent address can be automatically generated through the internal column address generator.

 

2. Why precharge?

Closing the active SDRAM bank is an end command. You can run a new command later. I think this is related to internal management of SDRAM. (I found this on the Internet. I don't feel details enough and I don't quite understand it)

 

3. Automatic refresh?

Dynamic Memory (Dynamic RAM) has a refresh problem. The automatic refresh method is used here to send a refresh command to the SDRAM at intervals.

 

4. SDRAM address line

In general, what is the SRAM, psram, and RAM used? Generally, how many IP address lines are there? Then we can calculate the addressing space, for example, there are 11 IP address lines, the addressing space is reduced by 1 to the power of 2. However, SDRAM uses separate addresses and line addresses, and the line and column address lines are reused. So sometimes we can see how big the addressing space is, but how many lines are there to look, haha. There are usually two bank lines in the SDRAM module, which are divided into four banks. In some processors, the two lines may be mapped to one or two of the address lines. Generally, a chip is used to write the configuration of the chip in the following way. For example, if it is 4 Meg x 4x16, the chip is 256 Mbits. Among them, 16 refers to 16 data lines, 4 in the middle is only divided into four banks, each bank is 4meg.

 

5. SDRAM Initialization

You must initialize the data before using the data after powering on the SDRAM. This operation process is a standard process. The process is as follows:

• Precharge
• Auto-Refresh
• Load mode register
• Normal read/write

Before entering the initialization command after power-on, a minimum latency of us is required (this is easy to meet ).

After the precharge command is entered, the A10 pin must be set to high because it must be precharge for all banks. Therefore, a read operation is performed after the precharge command, in this operation, the most important thing is that the address set in the addressing space of SDRAM must be A10.

After you enter the auto-Refresh command, you usually need to enter a few blank operations or read something. In any case, the latency is achieved so that the SDRAM has time to complete the refresh.

Then we need to set the mode register of the SDRAM, which usually sets the burst length, Cas, burst type, and operation mode, you can also set whether the SDRAM is working in a single read/write operation or a burst operation. This register is also set through the address line, therefore, after the load mode register command is issued, You need to perform an operation so that the value of the online outlet in the SDRAM address is the value you want to set. It is important to note that this operation is an 8-bit operation. Remember to remember.

After the mode register is set, the system enters the normal operation mode.

In fact, the specific operation should be set together with the SDRAM control module of the selected processor. The logic analyzer is used to analyze these initialization commands.

Here, we need to remind you that the CAS parameter is very important. There is also a need to refresh the SDRAM, so the refresh frequency can be calculated according to the manual, but it is also possible to set a higher level. It is often because of the frequency of running the SDRAM, but it can also work at a lower frequency. For example, if you work on a pcsag, it is also possible to reach 100. You do not need to modify the settings.

 

6. Basic read/write operations

The basic read operation of SDRAM requires the control line and address line to work together to issue a series of commands. Issue the bank activation command (active) and lock the corresponding bank address (given by ba0 and BA1) and line address (A0 ~ Given in A12 ). After the bank activation command, you must wait for the time greater than the trcd (Ras of SDRAM to the delay indicator of CAS) to issue the READ command. After Cl (CAS delay value) Clock, read data appears on the Data Bus in turn. At the end of the reading operation, you need to issue the precharge command to the SDRAM to close the activated page. Wait for the TRP time (precharge) command to close the activated page. After waiting for the TRP time (after the prechareg command, you can access this row again only after the TRP time is exceeded), you can start the next read and write operation. Only the burst mode (burst mode) is available for read operations on SDRAM. The burst length is 1, 2, 4, and 8.

The basic write operation of SDRAM also requires the control line and address line to work together to issue a series of commands. Issue the bank activation command (active) and lock the corresponding bank address (given by ba0 and BA1) and line address (A0 ~ Given in A12 ). After activating the bank command, you must wait for the time later than the trcd time to write the command. Write commands can be written immediately, and data needs to be written to the DQ (data line) in sequence. Delay twr time after the last data is written. Issue the pre-charging command to close the activated page. After waiting for the TRP time, you can expand the next operation. There are two types of write operations: burstable write and non-burstable write. The burst length is the same as the read operation.

 

7. Others

Sometimes we see that some data lines are switched over on the schematic diagram. In fact, this doesn't matter. The reverse connection is written into the reverse interface, but the reverse interface is read, there is no reverse attack twice.

Extended to the DDR, in fact, the DDR is a turtle shell added to the outside of the SDRAM. Therefore, the initialization is the same. Of course, DDR has a clock with an inverse clock frequency. Therefore, there are two 180-degree clocks with a phase difference. These two are generally generated using the same clock source, and the consistency will be better. There are two more dqs, which is also a time series requirement. Generally, the CPU control module has been set up. If the CPU you use does not include a control module, Use FPGA to implement a control module, you should study the timing.

In some processor control modules, due to the EMI settings, the address line ing relationship is complex, so the calculation is troublesome. Generally, if there is no ing, it is easy to operate.

 

 

 

 

 

There are two types of refresh operations: auto refresh (AR) and Self refresh (SR ). No matter what the refresh method is, you do not need to provide the line address information externally, because this is an internal automatic operation.

For Ar, there is a row address generator (also called refresh counter) inside the SDRAM to automatically generate row addresses in turn. Since refresh is performed on all the buckets in a row, column addressing is not required, or CAS is valid before Ras. Therefore, AR, also known as CBR (CAS before Ras, is refreshed by column positioning in advance. Since refresh involves all L-banks, all l-banks stop working during the refresh process, and each refresh takes nine clock cycles (pc133 standard ), after that, you can enter the normal working state. That is to say, during the nine clock periods, all the work commands can only be waited and cannot be executed. After 64 ms, refresh the same row again. Obviously, the refresh operation will definitely affect the performance of the SDRAM, but this is not feasible. It is also the dram (static memory, data can still be retained without refreshing) the cost of achieving cost advantages.

Sr is mainly used for data storage in sleep mode with low power consumption. The most famous application in this regard is STR (suspend to ram, sleep hangs in the memory ). When the AR command is issued, the cke is put into an invalid state and enters the SR mode. At this time, the system clock is no longer used, but the internal clock is refreshed. During the SR, all external signals except cke are invalid (no refresh command is required). You can exit the auto-Refresh mode and enter the normal operation status only when cke is valid again.

Parsing of the SDRAM Controller