The following board for my analog SWD interface is referred to as host, and the target MCU (i.e. the board I want to connect to) is referred to as target.
SWD Agreement
Therefore, the name Incredibles, serial Bus debugging interface. We need 3 wires connected to the target MCU, SWDIO,SWDCLK and GND.
The-swdio is a bidirectional data port, and the host to the target is transmitted.
-SWDCLK is the clock port, the host drive.
-gnd GND Foot.
First refer to "ARM Debug Interface V5" (Note: The document has an updated version, and the V5 version has been errata), some relevant protocol related to the relevant instructions have a relatively shallow understanding. Then we find a board with SWD interface, I first chose the stm32f030, because later can be made for the production line offline programmer, of course, then there are some problems, the following will explain.
Connected to the relevant physical connection, began to toss.
See the manual for a few relatively important timing instructions.
TRN-TRN: Line Turn-round, when the direction of data transmission on the bus changes (such as from Host->target to Target->host), you need to insert trn,trn into a CLK sequence, There is some doubt about the understanding of TRN.
Idle cycles: After a bus is complete, you can immediately enter the next bus operation or the bus into the idle state, you can insert the idle cycle. In this I used to send out 8 ' 0b0 ' to make the bus enter the idle state.
Parity: Check bit, this is relatively simple. Two content to verify the command header and verify the data. The command header is described below. The data check is to verify the 0b0-0b31, if the number of ' 1 ' is odd that the check bit is ' 0b1 ', if the number of ' 0b1 ' is even check bit for ' 0b0 '.
Having understood these, we'll look at the read-write command next.
Each read-write command will have a host->target header. Each data header is 1Byte.
-start the starting bit, which is always 1, which is also the target to determine the condition that the bus exits from the idle state.
-APNDP Select whether to access the DP register or the AP register.
-RNW Choose whether to read or write.
-a[2:3] The address of the DP or AP register, note that it is low in front. For example, register DP Register Select its address is 0x08, where A is C (0b1000), obviously A[2:3] is 01.
-praity check bit, it is APNDP, RNW and A[2:3] A total of 4 bit check bit.
-stop stop bit. is always 0.
-park This bit should always be described in 1,adi V5 as this bit is pulled by the bus, but due to the insufficient pull-up capability of the bus, target cannot recognize this 1. This erratum is described in Adi V5.2.
The Read command is composed of the data header +trn+ack+rdata+parity, but the actual operation found Trn this is ignored (so do not know whether the understanding of this Trn is wrong), and after sending the data header immediately read the ACK, to determine whether the target responds correctly.
The write command for the data header +trn+ack+trn+wdata+parity, in this case, in writing the command must consider the position of 2 Trn.
It is the most basic and simplest command to look at the protocol, which needs to be linereset first when the target is connected.
The implementation of the first to ensure that the host continuously send at least 50 "1", so that target line Reset, at least insert 2 idle, and then can read the target board IDR, determine the type of target.
Understand the whole, and then perform the operation verification, found that occasionally can have data ack, continue to view the manual, found that the need for JTAG and SWD switching operations. Check the manual to find the timing of the switchover operation as follows.
It can be simplified to linereset first, then send 0x79,0xe7 (high byte first), then Linereset again, then the IDR can be read. But found the problem, in this way can read to stm32f103 IDR, but stm32f030 not, on the ARM web site access to relevant information, found this.
The diagram above mainly says that in an earlier protocol it is necessary to send the following command in order to switch between JTAG and SWD. is to send 0x6d,0xb7, try the next, this can be successfully read to IDR. Puzzled is the STM32F0 series than F1 out to be late, incredibly use the old version of the protocol.
Now that you have access to IDR, you can then try to connect to the AHB-AP. Select with a DP register. Here, in order to be able to make the results obvious and accurate, I chose to read the IDR Register of AP 0XFC to get the features of the AP, because this data is read-only and exact.
The first thing to do is write the DP register select.
The specific description of select can be found in the Adi V5 manual, where there is a detour. There is a Apsel select bit in the Select Register, which selects the currently connected AP, which is not defined in detail in the manual. It was later found in another document that the value was 0x00,ahb-ap. Apbanksel to select the bank address to be accessed, such as the address of the IDR register is 0XFC, then its banksel is F, if it is a tar register, then its banksel is 0.
After connecting to the AHB-AP, you can do what you want to do. For example, I can read the independent ID of the MCU and it can be operated by MEM-AP. The MCU can also be erased or programmed.
Before programming, the MCU first enters the halt state, and then accesses the MCU related Flash control register to read and write.
In stm32f030 programming need to pay attention to stm32f030 Flash transmission mode, I did not adopt packet transmission mode.
Linereset Code
static void Swdlinereset (void)
{
U8 I;
Swd_out;
Swd_dio_h;
for (i=0;i<56;i++)
{
Swd_delay ();
Swd_clk_h;
Swd_delay ();
swd_clk_l;
}
}
Write Command header function
static void Swdsendbyte (U8 dat)
{
U8 I;
Swd_out;
for (i=0;i<8;i++)
{
if ((dat&0x80) ==0x80)
{
Swd_dio_h;
}
Else
{
swd_dio_l;
}
dat<<=1;
Swd_clk_h;
Swd_delay ();
swd_clk_l;
Swd_delay ();
}
}
Read a data function
Static u32 seqread (U8 cmd)
{
U32 dat=0;
U8 i=0;
Swdsendbyte (CMD);
swd_in;
for (i=0;i<3;i++)//ack here to handle the judgment
{
Swd_clk_h;
Swd_delay ();
swd_clk_l;
Swd_delay ();
}
dat=0;
for (i=0;i<32;i++)
{
dat=dat>>1;
Swd_clk_h;
Swd_delay ();
swd_clk_l;
if (swd_dii)
{
dat|=0x80000000;
}
Swd_delay ();
}
Parity
swd_in; Trn
for (i=0;i<2;i++)
{
Swd_clk_h;
Swd_delay ();
swd_clk_l;
Swd_delay ();
}
swd_dio_l;
Swd_out;
for (i=0;i<5;i++)
{
Swd_clk_h;
Swd_delay ();
swd_clk_l;
Swd_delay ();
Swd_clk_h;
Swd_delay ();
swd_clk_l;
Swd_delay ();
}
swd_in; Trn
return dat;
}
