PC interpretation 10: Introduction of the interrupt controller

Source: Internet
Author: User

Now we have realized that in the PC design, the CPU is not executed in full accordance with the program instructions. Sometimes the device is interrupted manually or randomly, allows the CPU to execute the corresponding interrupt processing program to build a more intelligent hardware and software system. So what kind of Interrupt Processing System has the top computer designers designed to achieve this demand? We try to interpret it all.

Interrupt Controller connection
First, let's look at the requirements. For the device, the simplest design is to provide a pin for the external device. If it is a high level, it means that I apply for interruption. If it is a low level, it means that there is no interruption request. The key is how to actively transmit the signal from this pin to the CPU? In the past, CPU instruction sets were used to read the I/O space to obtain these pin signals, the device actively transmits the pin interrupt signal across many bridges and bus between the peripherals and the CPU and finally notifies the CPU. This is one of the problems. In addition, many devices may need interrupt pins, such as the keyboard, mouse, and timer. If these pin signals are connected to the CPU, This seriously affects the CPU compatibility, versatility and conciseness. If this is not done, after the CPU receives the pin interruption signal, how can I know who sent the interrupted request? This is the second problem.

The problem looks complicated, but as long as everyone works together, nothing can be solved. First of all, the natural idea is to introduce an interrupt controller, which is best on the south bridge, Because I/O devices on the south bridge usually need to interrupt requests. The Interrupt Controller requires many interrupt signal pins to connect the interrupt request signal lines of the IO Device, so that the interrupt controller can sense the interrupt request of an external device immediately, it also knows which pin causes the interruption. At the same time, the interrupt controller also has a pin connected to the interrupt request line of the CPU, so that as long as the interrupt controller receives the interrupt request from the IO Device, it will immediately transmit the signal to the CPU, of course, this control signal needs to go through the bus between the North and South bridges to reach the north bridge and then through the front-end bus to reach the CPU,
Both the bus and the North Bridge need to be able to parse the interrupt request signal and transmit it. In this way, the CPU can sense that the peripheral needs to interrupt the request at a time.

It seems a lot easier to solve the problem because of the huge workload. So the CPU has only one pin. How does he know who triggered the interrupt request? Think too much, since the CPU has been sensed to interrupt, no matter who, after the induction directly through the command to ask the interrupt controller to know who is responsible for the interruption.

Interrupt number query
After the CPU knows who has interrupted the request, how can we find out where the interrupted interrupt processing program is? This requires software and hardware conventions. First, number the Interrupt Device, for example, Pin 1 of the interrupt controller, 1 of the interrupt device, and 2 of the interrupt device; then, the system prepares the interrupt handler for each interrupt to be added to the memory during initialization, provides an interrupt table, and stores the entry addresses of each interrupt handler in sequence, in addition, we can also default that the address of this interrupt table will always start at the physical address 0, so if the CPU encounters an interrupt request, we can get the interrupt number from the interrupt controller, then, find the interrupt handler entry in the interrupt table to proceed with the interrupt processing.

Early systems officially did this. The ibm pc/at 80x86 compatible host uses two cascade 8259a programmable interrupt control chipset into one interrupt controller to implement interrupt control data access for I/O devices, it can also provide independent interrupt control functions for 15 devices ,. During the initialization of the computer, the rom bios initializes two 8259a chips, the 15-level interrupt priority is assigned to the clock timer, keyboard, serial port, print port, floppy disk control, coprocessor, hard disk, and other devices or controllers. At the same time, the memory starts at 0*000 ~ Create an interrupt vector table in the 0xfff area. However, these settings violate Intel's requirements (which will be described later), so the Linux operating system re-sets the 8259a during kernel initialization.

Interrupt vector allocation
When a PC is powered on, the hardware interruption request number shown in the figure is set by the rom bios to the corresponding interrupt vector Number shown in table 1. The Linux operating system does not directly use the interrupt vector numbers set by default for these PCs. When the Linux system performs initialization, it resets the correspondence between the interrupt request number and the interrupt vector number.

Table 1: hardware Request Handling interrupt number set by rom bios during boot

Interrupt request no. BiOS interrupt number Purpose Interrupt request no. BiOS interrupt number Purpose
Irq0 0 × 08 (8) 8253Hz clock interruption Irq8 0 × 70 (112) Real-time clock interruption
Irq1 0 × 09 (9) Keyboard interrupt Irq9 0 × 71 (113) To int 0x0a
Irq2 0x0a (10) Slave chips Irq10 0 × 72 (114) Retained
Irq3 0x0b (11) Serial Port 2 Irq11 0 × 73 (115) Reserved (Network Interface)
Irq4 0x0c (12) Serial Port 1 Irq12 0 × 74 (116) PS/2: The mouse is interrupted.
Irq5 0x0d (13) Parallel Port 2 Irq13 0 × 75 (117) Mathematical coprocessor interruption
Irq6 0x0e (14) Floppy disk drive Irq14 0 × 76 (118) Hard Disk interruption
Irq7 0x0f (15) Parallel Port 1 Irq15 0 × 77 (119) Retained

At the same time, we can see that early PC manufacturers have made great efforts to design the system and develop the first-layer BIOS program, and assemble all system components into an organic whole, provide a good system for external users. Thanks to the openness of this technology, PC technology has developed rapidly.

Contact Us

The content source of this page is from Internet, which doesn't represent Alibaba Cloud's opinion; products and services mentioned on that page don't have any relationship with Alibaba Cloud. If the content of the page makes you feel confusing, please write us an email, we will handle the problem within 5 days after receiving your email.

If you find any instances of plagiarism from the community, please send an email to: info-contact@alibabacloud.com and provide relevant evidence. A staff member will contact you within 5 working days.

A Free Trial That Lets You Build Big!

Start building with 50+ products and up to 12 months usage for Elastic Compute Service

  • Sales Support

    1 on 1 presale consultation

  • After-Sales Support

    24/7 Technical Support 6 Free Tickets per Quarter Faster Response

  • Alibaba Cloud offers highly flexible support services tailored to meet your exact needs.