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Basic flow: Pre-preparation->PCB structure design->PCB layout-cabling optimization and screen-and network and DRC inspection and structural inspection-plate.1. Pre-preparation
Software tools + corresponding libraries (be sure to accumulate, form your own schematic library and packaging library)
Component Library Requirements:
1. Pin Properties and PCB counterpart
2. Simple, clear and easy to understand
For example, when drawing a chip on the schematic diagram is best to see the size of the chip shape and 1 feet, etc., easy in the welding debugging control.
Size requirements, the pad is larger than the datasheet, note the usual 1206 0805 0603 0402 to avoid mixing. The hole is a little bigger.
(In principle, first do the packaging library and then do the principle library)
Smd:surface Mount Devices Surface mount
Bga:ball grid array Spherical contact lattice column
Sip:single In-line Package single row inline
Dip:dual In-line Package Dual-row inline packages
Qfp:quad Flat package four side pin offset flat
Four-sided pin flat package. Pin Center distance 1.0mm, 0.8mm, 0.65mm, 0.5mm, 0.4mm, 0.3mm and many other specifications.
Japan will pin the center distance of less than 0.65mm QFP called QFP (FP). But now the Japanese electronics machinery industry will be on the QFP
The form factor was re-evaluated. The PIN center distance is not differentiated, but according to the package body thickness is divided into
QFP (2.0mm~3.6mm thick), LQFP (1.4mm thick) and TQFP (1.0mm thick) three kinds.
In addition, some LSI manufacturers to the pin center distance of 0.5mm of QFP is specifically known as the contraction type QFP or SQFP, VQFP.
But some manufacturers to the pin center distance of 0.65mm and 0.4mm QFP also known as SQFP, to make the name slightly mixed
Fqfp:fine Pitch Quad flat package Kohiki Foot Center distance qfp,e<0.65mm
Lqfp:low Profile Quad Flat package thin QFP, body thickness =1.4mm
TQFP: Body Thickness =1mm
Cqfp:ceramic Quad Flat Pack Ceramic QFP
QFN: No pinout, also known as LCC, PCLC, P-LCC, etc. e=1.27mm, 0.65mm, 0.5mm,
Sop:small out-line Package Small form factor, e=1.27mm,8~44 feet
Ssop:shrink Small-outline Package narrow pitch small form factor plastic seal, e<1.27mm, commonly used e=0.65mm
Tsop:thin Small Outline Package miniature wafer type, body thickness <1.27mm
Tssop:thin Shrink Small Outline Package
SOJ: Plastic J-shaped wire package
Sot:small out-line transistor small form factor transistor, e=0.95mm2.PCB Structural Design
According to the determined board size and the mechanical positioning, the PCB design environment to draw the PCB surface, and according to positioning requirements to place the required connector, keys/switches, screw holes, assembly holes and so on. and to fully consider and determine the wiring area and non-wiring areas (such as the size of the screw hole around the area is non-wiring areas).3.PCB layout
①. According to the reasonable electrical performance zoning, generally divided into: Digital circuit area (that is, fear of interference, and interference), analog circuit area (fear of interference), Power Drive zone (interference source);
②. Complete the same function of the circuit, should be placed as close as possible, and adjust the components to ensure that the most concise connection, at the same time, adjust the relative position between the functional blocks to make the connection between the most concise;
③. For large-quality components should consider the installation position and installation strength, heating elements should be separated from the temperature-sensitive components, when necessary, should also consider the thermal convection measures;
④. I/O drive parts as close as possible to the edge of the printing plate, near the lead connector;
⑤. The clock generator (e.g. crystal or TCXO) should be as close as possible to the device using the clock;
⑥. In each integrated circuit of the power input between the foot and the ground, need to add a decoupling capacitor (generally high-frequency performance of the single-stone capacitor); When the circuit board space is more dense, you can also add a tantalum capacitor around several integrated circuits.
The advantages of tantalum capacitors: capacity Change by the external environment, small size, wide range of use temperature, high temperature and long life, insulation resistance, leakage current small and small capacity errors are the advantages of tantalum capacitors, and can be extremely severe under the conditions of work.
Monolithic capacitance: Also known as porcelain dielectric capacitance, this type of capacitance has a large capacity, small size advantages, but also has a strong high temperature performance. It is relatively one of the many advantages of capacitance type.
⑦. Relay coil to add discharge diode (1n4148);
⑧. Layout requirements to be balanced, orderly, not top-heavy or Yitou
Must test the road components of the size of the package height relative position, modify the device placement, make it neat and beautiful.4. Cabling
Cabling is the most important process in the entire PCB design. This will directly affect the performance of the PCB board.
①. In general, the power line and ground should be routed first to ensure the electrical performance of the circuit board. Within the allowable range, as far as possible to widen the power supply, ground width, preferably ground than the power line, their relationship is: Ground > power line > Signal line, usually the signal line width is: 0.2~0.3mm, the most fine width up to 0.05~0.07mm, power cord is generally 1.2~2.5mm. The PCB of the digital circuit can be used to form a circuit with wide ground wire, that is, to make a net to use (analog circuit of the ground can not be used)
②. Prior to the strict requirements of the line (such as high-frequency line) wiring, input and output side should avoid adjacent parallel, so as not to produce reflection interference. If necessary, ground insulation should be added, two adjacent layers of the wiring to each other perpendicular, parallel prone to parasitic coupling.
③. The oscillator shell is grounded, the clock line should be as short as possible, and cannot be attracted everywhere. Under the clock oscillation circuit, the special high-speed logic circuit part should increase the area of the ground, and should not take other signal lines, so as to make the surrounding electric field approaching 0;
④. Use 45o of polyline cabling as much as possible, not 90o polylines, to reduce the radiation of high-frequency signals (high-demand lines also use double arcs)
⑤. Any signal line should not form a loop, such as unavoidable, the loop should be as small as possible, the signal line through the hole should be as little as possible;
⑥. The key lines are as short and thick as possible, with a protective ground on both sides.
⑦. When transmitting the sensitive signal and the noise field with the flat cable, the "ground-signal-ground" method should be used to elicit the signal.
⑧. Test points should be reserved for critical signals to facilitate production and maintenance testing
⑨. After the schematic wiring is completed, the cabling should be optimized; At the same time, after the initial network inspection and the DRC inspection is correct, the non-wiring area for ground filling, with a large area of copper layer for ground use, on the printed board is not used on the place is connected to the ground as ground. Or made of multilayer board, power, ground each occupy a layer.
In general, the signal line width is 0.3mm (12mil), the power cord width is 0.77mm (30mil) or 1.27mm (50mil), and the distance between the line and the wire and the pad is greater than or equal to 0.33mm (13mil), in practical applications, the conditions should be considered to increase the distance;
High cabling density, you can consider (but not recommended) using IC foot to walk two lines, the width of the line is 0.254mm (10mil), the line spacing is not less than 0.254mm (10mil). In special cases, when the device pins are tight and the width is narrower, the line width and line spacing can be reduced as appropriate.
②. Pad (PAD)
The basic requirements of pad (PAD) and Transition hole (VIA) are: the diameter of the disc is greater than 0.6mm, for example, general-purpose pin resistors, capacitors and integrated circuits, such as disk/hole size 1.6mm/0.8mm (63mil/32mil), sockets, pins and diodes 1n4007, Use 1.8mm/1.0mm (71mil/39mil). In practical application, the size of the actual components should be determined according to the conditions, the appropriate enlargement of the size of the pad;
PCB Board design components installed aperture should be greater than the actual size of the component pin 0.2~0.4mm about.
③. Over Hole (VIA)
Generally 1.27mm/0.7mm (50mil/28mil);
When the wiring density is high, the hole size can be suitably reduced, but not too small, you can consider using 1.0mm/0.6mm (40mil/24mil).
④. Clearance requirements for pads, wires, vias
PAD and VIA: ≥0.3mm (12mil)
Pad and pad: ≥0.3mm (12mil)
PAD and Track: ≥0.3mm (12mil)
Track and track: ≥0.3mm (12mil)
At higher densities:
PAD and VIA: ≥0.254mm (10mil)
Pad and pad: ≥0.254mm (10mil)
PAD and Track: ≥0.254mm (10mil)
Track and track: ≥0.254mm (10mil)5. Cabling Optimization and screen printing
The general design experience is: the time to optimize cabling is twice times the initial wiring time. Feel that there is no place to change, you can lay the copper (Place->polygon Plane).6. DRC inspection and structural inspection of the network
First, in determining the circuit schematic design without error, the generated PCB network files and schematic network Files physical connection network Check (Netcheck), and according to the output file results in a timely manner to correct the design, in order to ensure the correctness of the wiring connection relationship;
After the network check correctly passed, the PCB design for the DRC check, and according to the output file results in a timely manner to correct the design to ensure the electrical performance of PCB wiring. Finally, the mechanical installation structure of PCB should be checked and confirmed.7. Plate making
PCB Design Process
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