PCB layout Guide

Address: http://blog.csdn.net/qq736934266/article/details/3582764

 

 

1. General rules
1.1 Pre-division of digital, analog, DAA signal cabling areas on the PCB.
1.2 numbers, analog components and corresponding cabling should be separated and placed in their respective cabling areas as far as possible.
1.3 high-speed digital signal cabling as short as possible.
1.4 The sensitive analog signal must be as short as possible.
1.5 reasonably allocate power supplies and locations.
1.6 dgnd, agnd, and field separation.
1.7 power supply and critical Signal Distribution Using Wide line.
1.8 The digital circuit is placed near the parallel bus/serial DTE interface, and the DAA circuit is placed near the telephone line interface.
2. Component placement
2.1 In the system circuit diagram:
A) Dividing digital, analog, DAA circuits and their related circuits;
B) number, analog, and hybrid digital/analog components are divided in each circuit;
C) locate the power supply and signal pins of each IC chip.
2.2 preliminarily divide the cabling area of the digital, analog, and DAA circuit on the PCB Board (generally 2/1/1 ), numbers, analog components and their corresponding cabling should be kept as far away as possible and limited to their respective wiring areas.
Note: When the DAA circuit occupies a large proportion, there will be a large number of control/status signals going through the wiring area, which can be adjusted according to local rules, such as device spacing, high voltage suppression, and current limit.
2.3 After preliminary division, the components will be placed from ctor and jack:
A) Leave plug-ins around ctor and Jack;
B) Leave room for power supply and ground cabling around components;
C) Leave the corresponding plug-ins around the socket.
2.4 first place hybrid components (such as modem devices, A/D and D/A conversion chips ):
A) Determine the placement direction of components and try to direct the digital signal and analog signal pins to their respective wiring areas;
B) Place components at the junction of the digital and analog signal cabling area.
2.5 place all simulators:
A) Place analog circuit components, including the DAA circuit;
B) The simulator components are close to each other and placed on the PCB, including the txa1, TXA2, Rin, Vc, and vref signal cabling side;
C) Avoid placing high-noise components around txa1, TXA2, Rin, Vc, and vref signals;
D) For serial DTE module, dte eia/TIA-232-E
The receiving/driver of the series of interface signals should be close to connector and stay away from high-frequency clock signals to reduce/avoid noise suppression devices added to each line, such as resistance loops and capacitors.
2.6 placement of digital components and decoupling capacitors:
A) centralized placement of digital components to reduce cabling length;
B) the decoupling capacitor of 0.1uf is placed between the power supply and ground of the IC, and the connection line is as short as possible to reduce EMI;
C) For parallel bus modules, components are closely connected
Ctor ctor edge is placed to comply with the application bus interface standards. For example, the ISA bus strip length is limited to in;
D) For the serial DTE module, the interface circuit is close to connector;
E) The crystal oscillator circuit should be close to its driver whenever possible.
2.7 The Ground Wires in various regions are usually connected with 0 ohm resistors or bead at one or more points.
3. Signal cabling
3.1 When the modem signal goes offline, the signal line that is easy to produce noise and the signal line that is easily disturbed should be kept away as far as possible. If this cannot be avoided, neutral signal lines should be used for isolation.
The following table lists the signal pins that are easy to generate noise by modem, neutral signal pins, and interference-prone signal pins:
========================================================== ======================================
| Noise source | neutral | Noise
Sensitive

　

----------- + ---------------- + -----------------
VDD, Gnd, agnd |, |

----------- + ---------------- + -----------------
Crystal | 52,53 |

----------- + ---------------- + -----------------
Reset | 35 |

----------- + ---------------- + -----------------
Memory bus | 1-6, 9-10, 12-13 |
| 43-50, 58-68 |

----------- + ---------------- + -----------------
NVRAM | 39,42 |

----------- + ---------------- + -----------------
Telephone | 7-, | 24-25, 30, 32-33

----------- + ---------------- + -----------------
Audio |-29

----------- + ---------------- + -----------------
Serial DTE | 40-41 | 11,14-22,55-57 |

========================================================== ======================================

========================================================== ======================================
| Noise source | neutral | Noise
Sensitive

----------- + ---------------- + -----------------
VDD, Gnd, agnd |, |

----------- + ---------------- + -----------------
Crystal | 52,53 |

----------- + ---------------- + -----------------
Reset | 35 |

----------- + ---------------- + -----------------
Memory bus | 1-6, 9-10, 12-13 |
| 43-50, 58-68 |

----------- + ---------------- + -----------------
NVRAM | 39,42 |

----------- + ---------------- + -----------------
Telephone | 7-, | 24-25, 30, 32-33

----------- + ---------------- + -----------------
Audio |-29

----------- + ---------------- + -----------------
Parallel bus |--41 |
| 55-57 |

========================================================== ======================================
3.2 digital signal cabling should be placed in the digital signal cabling area as much as possible;
Simulate signal cabling should be placed in the analog signal cabling area as much as possible;
(Separate cabling can be pre-defined to prevent cabling from going out of the cabling area)
The digital signal line is perpendicular to the analog signal line to reduce cross coupling.
3.3 Use isolated cabling (usually in the ground) to limit the analog signal cabling to the analog signal cabling area.
A) The cabling area of the analog area is arranged on both sides of the PCB with a line width of 50-mil;
B) The cabling area of the digital area is arranged on both sides of the PCB, with a line width of 50-mil and a mil side of the PCB.
3.4 parallel bus interface signal line width> 10mil (generally 12-15mil), such as/HCs,/HRD,/hwt,/reset.
3.5 analog signal line width> 10mil (generally 12-15 mil), such as micm, micv, spkv, Vc, vref, txa1, TXA2, rxa, telin, and telout.
3.6 All other signals should be as wide as possible, with a line width greater than 5mil (generally 10mil), and components should be as short as possible (the device should be placed in advance ).
3.7 bypass capacitor to the line width of the corresponding IC> 25mil, and try to avoid using through holes.
3.8 signal lines through different regions (such as typical low speed control/status signals) should be at one point (preferred) or two points through the isolation ground. If the cabling is only on one side, the isolating ground can go to the other side of the PCB to skip the signal cabling and maintain continuity.
3.9 high frequency signal line to avoid 90 degrees angle bending, should use smooth arc or 45 degrees angle.
3.10 high-frequency signal cabling should reduce the use of through-hole connections.
3.11 all signal strip away from the crystal oscillator circuit.
3.12 for high-frequency signal cabling, a single continuous cabling should be adopted to avoid extending several segments from one point.
3.13 In The DAA circuit, leave at least 60 mil space around the perforation (all layers.
3.14 clear the ground loop to prevent unexpected current feedback from affecting the power supply.

4. Power supply
4.1 determine the power connection relationship.
4.2 In the digital signal cabling area, the 10uf electrolytic capacitor or the TA capacitor and the 0.1uf porcelain chip capacitor are connected in parallel to the power supply/ground. place one position at the PCB power entry end and the far end to prevent noise interference caused by power spikes.
4.3 pairs of Dual-panel, in the same level of the power circuit, the circuit is surrounded by a power line of mil on both sides. (The other side must be processed in numbers)
4.4 generally, the power supply goes offline first, and then the signal goes offline.
5. Location
In the 5.1 double panel, numbers and analog components (except DAA) are filled with areas that are not used at and below digit or analog areas, and areas of the same type are connected together at each layer, different levels of the same region are connected through multiple passing holes: the modem dgnd pin is connected to the digital region, and the agnd pin is connected to the analog region; the digital and analog areas are separated by a straight gap.
In the 5.2 4-board, digital and analog areas are used to cover digital and analog components (except DAA); the modem dgnd pin is connected to the digital area, and the agnd pin is connected to the analog area; the digital and analog areas are separated by a straight gap.
5.3 If EMI Filters are required during design, a certain amount of space should be reserved at the interface outlet end. The vast majority of EMI devices (bead/capacitor) can be placed in this area. unused areas are filled in area, A shielded shell must also be connected.
5.4 Power Supply of each function module should be separated. Function modules can be divided into parallel bus interface, display, digital circuit (SRAM, EPROM, modem) and DAA. The power supply/location of each function module can only be connected at the source point of the power supply/ground.
5.5 for the serial DTE module, the decoupling capacitor is used to reduce power coupling, and the same processing can be performed on the telephone line.
5.6 The ground wire is connected by a single point. If possible, bead is used. If EMI suppression is required, the ground wire is allowed to be connected elsewhere.
5.7 all ground wires should be as wide as possible, 25-50 mil.
5.8 ensure that the capacitance of all IC power supplies/locations is as short as possible without passing through holes.
6. crystal oscillator circuit
6.1 All cables connected to the crystal oscillator input/output end (such as xtli and xtlo) should be as short as possible to reduce the effect of noise interference and distribution capacitance on crystal. The xtlo cabling should be as short as possible, and the bending angle should not be less than 45 degrees. (Because xtlo is connected to a drive with fast rising time and large current)
There is no ground layer in the 6.2 double panel, and the crystal oscillator capacitive ground should be connected to the device using a short line as wide as possible
The dgnd pin closest to the crystal oscillator, and the hole passing should be minimized.
6.3 If possible, crystal shell grounding.
6.4 is connected to the xtlo pin and the crystal oscillator/capacitor node with a 100 ohm resistance.
The 6.5 crystal oscillator capacitor is directly connected to the modem's Gnd pin. Do not use the ground area or ground line to connect the capacitor to the modem's Gnd pin.
7. Independent modem design using EIA/TIA-232 Interface
7.1 use a metal housing. In case of plastic housing, metal foil or conductive material should be pasted inside to reduce EMI.
7.2 put choke in the same mode on each power cord.
7.3 components placed together and closely connected to EIA/TIA-232 interface ctor.
7.4 all EIA/TIA-232 devices are separately connected to power supplies/locations from power sources. The source point of the power supply/location should be the output end of the power supply input end or voltage regulator chip on the board.
7.5 EIA/TIA-232 cable signal ground to digital ground.
Less than 7.6 EIA/TIA-232 cable shielding do not need to be connected to the modem housing; Blank connection; through bead received digital; EIA/TIA-232 cable near the modem housing placed a magnetic ring directly connected to the digital place.
8. The VC and vref circuit capacitor cables should be as short as possible and located in neutral areas.
8.1 10 uf vc electrolytic capacitor the positive electrode and the 0.1 uf vc capacitor are connected to the modem VC pin (pin24) through independent cabling ).
The 8.2 10 uf vc electrolytic capacitor and the 0.1 uf vc capacitor are connected to the modem's agnd pin (pin34) through bead ).
The 8.3 10 UF vref electrolytic capacitor is connected to the vref pin (pin25) of the 0.1 uf vc capacitor through independent cabling ).
The 8.4 UF vref electrolytic capacitor and the 0.1 uf vc capacitor are connected to the modem's VC pin (pin24) through independent cabling. Note that they are independent from the 8.1 strip.
Vref ------ + -------- +
201710u 00000.1u
VC ------ + -------- +
201710u 00000.1u
+ -------- + -----~~~~~ --- + Agnd
Bead should meet the following requirements:
MHz, impedance = 70 W ;;
Rated current = 200mA ;;
The maximum resistance is 0.5 W.
9. Telephone and handset Interfaces
9.1 place choke at the tip and ring interfaces.
The 9.2 telephone line decoupling method is similar to the power supply decoupling method, using methods such as adding an inductor combination, choke, and capacitor. However, telephone line decoupling is more difficult and worth noting than power supply decoupling. The general practice is to reserve the positions of these devices for adjustment during performance/EMI testing and authentication.
9.3 tip and ring line to digital place high voltage filtering capacitor (0.001 UF/1kv ).