PCI bar space prefetch and non-prefetch

PCI bar space is divided into two types: ioresource_io (non-prefetch) and ioresource_mem (pre-Fetch). Generally, the bar space must be set to ioresource_io. For bar space, to set it to ioresource_mem;

 

So why do we need to distinguish between two types of space?

The so-called prefetch focuses on the word "Fetch", which depends on the difference between reading Io registers and RAM memory.

 

 

 

Ldd3

 

If the memory area is identified as prefetch, the CPU can cache its content and optimize it for all types. non-prefetchable memory access, on the other hand, cannot be optimized because each access may have a marginal effect,
It is like an I/O port. peripherals that map their registers to a memory address range declare that this range is non-prefetch, while some video memory such as the PCI board can be prefetch.

 

Web Search

 

In some applications, we will encounter"Prefetch"Memory concept,PrefetchSex refers to the storage spacePrefetchCapability. If the read operation has no side effects (that is, reading data from Ram does not damage the data), it is called the memory space.Prefetch. If necessary, the byte write operation can be combined into a dual-word write operation.PrefetchThe read address and storage status will not be changed once. The CPU can cache its content and optimize it for all types ,.Non-Prefetch"The memory is similar to the first-in-memory address. After reading data, the first-in-first-out pointer changes. in addition, I/O in the interrupt state is also reflected in the memory. After reading this memory, the interrupt mark may be cleared, and so on. Therefore, the CPU cannot cache this memory address.

 

 

64h16 datasheet register Definitions

 

 

Hwinit

RC

 

In the Embedded ARM processor, there is no special Io read instruction, but the access register is read and written by the memory. Therefore, there is still a memory ing IO Device in the PCI space,
Different Features of PCI prefetch memory device and memory ing IO Device:

Prefetch memory device features:
1) Multiple reads and writes generate the same data;
2) bytes can be merged in the forwarding write buffer;

For memory ing I/O devices, none of the above two features apply, because:
1) For some status registers, reading may cause the status bit to be cleared; for FIFO, reading the header data will cause the subsequent data to be automatically moved;
2) bytes cannot be merged in the forwarding buffer of the bridge chip;