PCI bus Study Notes

Reprinted please indicate the source: http://blog.csdn.net/lg2lh/article/details/8042008

The basic protocol of PCI is not introduced here. Because the General chip protocols are well integrated, I only need to know about them. I don't need to know the protocol too much because I don't have to do chips.

The explanation here is based on the PLX 9054 (9052) chip. I am only a beginner and hope to criticize and correct it.

I. Address ing and Data Transmission

The middle part is the internal structure of 9054, and 9054 actually acts as a"Bridge"Is called"Bridge film technology". In fact, the role of 9054 is to take the local bus end management address and the PCI bus end management address one by one, that is, the so-calledAddress ing,The PCI bus and the CPU management memory address of the PC are one-to-one, so that the bridge is realized: CPU address <=> PCI address <=> local address.

Generally, the system PCI address is part of the CPU address. For more information about the relationship between the PCI address and the system address, see the blog article http://blog.csdn.net/lg2lh/article/details/8042629.

The above only describes the relationship between the local bus and the PCI bus and the CPU bus, but the actual function of the PCI technology is to transmit data. The internal structure shows that 9054 has no storage unit and only a few FIFO instances. How does the system transmit data? We all know that an address corresponds to a bucket, which can be identified by the above address ing, PCI chip 9054 actually transfers the data from the external storage space managed by the local bus address to the memory space corresponding to the pci bus address and the memory space of the CPU. Or, you can transfer data in the memory to the external address space managed by the local bus. The storage space managed by the local address bus is generally provided by our control chip, such as FPGA or MCU.

Ii. Basic knowledge of PCI9054

The PCI9054 pins are mainly divided into three parts: PCI bus interface, local bus interface, and serial EEPROM bus interface.

The data width of the local bus is 32 bits, and the clock speed is up to 50 MHz. The following describes the functions of the three bus, as shown in the following figure.

PCI bus interface: responsible for communicating with the PCI bus of the PC. It must be connected to the Gold finger of the PCI board. For 32-bit systems, there are a total of 120 gold fingers and signal lines, 60 each on both sides of a and B, 1-62, 50, 51, no Gold finger pin, a total of 60.

Local Bus Interface: it is mainly responsible for local address data management and is connected to peripheral CPLD or MCU.

Serial EEPROM bus interface: it is mainly responsible for all the registers of PCI9054, and writes the register configuration to the EEPROM. After the PCI device is powered on, it loads the eeprom content and completes the register configuration of PCI9054. It mainly includes PCI configuration registers, PCI local configuration registers, execution time registers, DMA configuration registers, and i2o Information registers (Message Queue registers ?).

 

There are three main modes for data transmission between the PCI bus and the local bus of PCI9054: master mode, slave mode, and DMA mode.

The local bus also has three modes: M, C, and J. C mode is often used: Address Data BusNon-reusableMode.

 

Iii. Relationship between registers of PCI9054

The first section mentioned the ing between the PCI bus and the local address, and the PCI ing between the PCI address and the PC memory space. Generally, the PC thinks that the PCI address is the memory space address.9054 the solution is to match the address space managed by the local bus with the memory address.The following describes how to configure the ing through the 9054 register.

You need to understand that it is through the plx_mon software to configure the register content as required, and then burn the data into the EEPROM, a total of 17 words.

First, let's take a look at what are the main registers of PCI9054. As mentioned above, there are five main parts: PCI configuration registers, PCI local configuration registers, execution time registers, and DMA configuration registers, i2o Information Register (Message Queue register)

 

1. PCI configuration register: Registers related to the PCI bus, such as device ID, supplier ID, category code, version, system supplier ID, and subsystem ID. The PCI device ID is 9054, the supplier ID is 10b5, and the category code is 0680. The corresponding registers are as follows:

This section describes the last four registers. These four registers are used to map the local bus-related registers to the PCI bus, and the ing of the address space managed by the local bus on the PCI bus. All four registers areConfigured by the system and cannot be configured through the EEPROM. Among them, pcibar0 and pcibar1 are better understood than others. They map local bus configuration registers, DMA registers, and execution registers to the corresponding memory space,The configured value is their starting address in the memory space..

The following describes the pcibar2 and pcibar3 registers.Two-part address space, Space0 and space1. Pcibar2 and pcibar3 map the two parts to the pci bus address, that is, to map the two spaces to the memory space of the PC. The Configuration value of pcibar2 is the starting address of the local bus-side space0 space mapped to the PCI memory space. The configuration value of pcibar3 is the starting address of the local bus-side space1 space mapped to the PCI memory space. The actual addresses and ranges of space0 and space1 on the local bus end are determined by the local configuration register. The following describes local configuration registers.

 

2. Local configuration register

Registers corresponding to space0.

Las0rr:Space0 base address register. This register corresponds to the pcibar2 register of the PCI bus, that is, the FPGA (MCU) at the local end isAsk pcibar2 about the PCI memory space through the memory address..

If las0rr is set to 0x80000001 at this time, and pcibar2 is set to 0xe7000000, then the issue of the PCI space 0xe7000000 will be mapped to the issue of the local space 0x80000001. The following figure shows the ing legend.

Las0ba: The address range of space0 space. The value in the EEPROM isComplement of the actual RANGE.

 

Las1rr and las1ba are the same as the above two. They are only used to map the starting address and range of space1 space.

 

3. DMA configuration register

4. Register configuration method

Finally, we will introduce the eeprom configuration characters, including the long loading mode and the extra long loading mode. When the long loading mode contains 17 long words, the extra long loading mode contains 22 long words. MediumLas1rr and las1ba registers are configured in extra long loading mode.The most important configuration for plx9054 is to complete the configuration of PCI registers and local registers. 17 long words and 22 long words detailed load content such as the following table.

PCI bus Study Notes