PCIE Learning Note---TL (1)

Chapter 5:TLP elements (Details of TLP)

Chapter 6:flow Control

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Digest (end to end CRC, ECRC)

HDR + DATA + DIGEST = TLP

Seq Num + TLP + crc:dll

STP + DLL + END:PL

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1.

Flow-control buffers is maintained separately (VC each has its own flow control BUFFER)

PCIe supports up to 8 Virtual Channels

2.

credit-based mechanism

Initialization Stage & Run-time stage (using Flow Control dllps to updates) (initial and runtime phases)

3.

VC Flow Control Buffer Category:

Posted Transactions:memory writes and messages

Non-posted transactions:memory reads, configuration reads and writes, and Io reads and writes

Completions:read and write completions

Each category was separated into header and data portions

PH, PD, NPH, NPD, CPLH, CPLD (classification of VC buffer)

4.

Link up signal from physical layer to data link layer (physical Layer link training completed) (Link up signal)

5.

Dlcmsm:data Link Control and management state machines (DLCMSM states machine, and each state's jump condition and the action of each State)

Dl_inactive--Dl_init (Fc_init1, Fc_init2)--dl_active

Reset--dl_inactive (Action:dl_down signal to both DLL and TL)--dl_init sub-state (condition:phy link up)

Fc_init1 (Action:sequence of 3 InitFC1)

Fc_init2 (Action:sequence of InitFC2, confirm FC initialization have succeeded at the sender, dl_up to TL)