Pentium III Processor Single instruction multiple data Flow extension instruction (1)

Key words:

Pentium, processor, single instruction multiple data flow extension instruction, SSE, instruction set

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With the release of the Intel Pentium III processor, many new features have been brought to the program designers. With these new features, programmers can create better products for users. Many of the new features of Pentium III and Pentium III Xeon (Xeon processors) enable her to run faster than the Pentium II and Pentium II Xeon processors, which include a processor serial number (unique Processor ID) and the Add SSE processor instruction set, these new instruction sets are like the MMX instruction set added by Pentium II on the basis of classic Pentium.

In this article, we will show you the Pentium III processor and her new features, and will focus on the new instruction set for the Pentium III processor.

1.Pentium III Processor Overview

In February 1999, Intel released her latest processor Pentium III processor, which, like the previous launch of new processors, is the main performance improvement. Intel has consistently followed Moore's law in releasing her new processor, that is, the processor's speed will increase by one time per 18 months (the processor speed doubles every months), but the Pentium III processor is no better than Pentium The speed of II is increased by one time, while the Pentium II and Pentium II Xeon processors run at 333mhz~400mhz, Pentium III is only operating in 450mhz~550mhz, and the processor speed is not much improved, But the improvement in performance is obvious.

Essentially, the Pentium III processor is simply a Pentium II processor running at a higher speed, with additional new instruction sets: Streaming SIMD Extensions (single instruction multiple data flow extension instruction set, or SSE). The addition of these new instruction sets does not affect the original program, because the Pentium III processor uses a IA-32 architecture that is completely compatible with the original Pentium II processor.

If the speed of the Pentium III processor is no higher than that of Pentium II, why do we have to buy her?

New features of 2.Pentium III processors

The Pentium III processor adds two interesting and useful new features: Processor serial number (processor serial) and SSE instruction set. Since the serial number of the Pentium III processor involves user privacy controversy, in order to avoid this controversy, Here we will focus on the new SIMD instruction set on the Pentium III processor.

SSE contains the initials of a SIMD, which is the acronym for the first letter of single instruction multiple data. Typically, the processor can only process one data at a single instruction cycle, which is known as A/z instruction Single data, abbreviated as Sidi. Unlike Sidi, if the processor has SIMD capabilities, then she can process multiple data at the same time in one CPU instruction cycle.

3.MMX vs SSE

Both MMX and SSE are extensions of instruction sets that are added on the basis of the original processor instruction set, which are SIMD (single instruction multiple data) directives, and differ in the types of data they handle. MMX can only support SIMD on integers, while SSE instructions increase SIMD support for single-precision floating-point numbers. MMX is capable of simultaneous integer operations of 2 32 bits, while SSE can operate on 4 32-bit floating-point numbers.

One of the main differences between MMX and SSE is that MMX does not define a new register, SSE defines 8 new 128-bit registers, each of which can hold 4 single-precision floating-point numbers (32 bits long), and they are sorted in registers in the following figure 1.

Figure I: New data type arrangement

Here is a question, since MMX does not define a new register, what registers do she have to operate? In fact, MMX is shared with the original floating-point registers. A floating-point register is 80 bits long and her low-end 64 bits are used as MMX registers. In this way, An application cannot perform a floating-point operation while executing a MMX instruction. At the same time, the processor spends a lot of clock cycles to maintain the switching of the register state from the MMX operation to the floating-point operation. The SSE instruction set does not have these limitations. Because she defines a new register, The application can perform a floating-point SIMD (SSE) operation while performing an integer SIMD (MMX), and SSE can also perform SIMD operations at the same time as a non-SIMD operation of floating-point numbers.

The MMX and SSE registers are arranged as shown in Figure 2 below. Figure 2 (a) is a case where the MMX and floating-point numbers share a register, and figure 2 (b) is an independent register arrangement for SSE.

Figure II: MMX and SSE registers

The MMX and SSE registers have one thing in common: there are 8 registers. The MMX register is named Mm0~mm7,sse's register name is XMM0~XMM7.