PLL phase-locked loop for FPGA

• The PLL is actually a negative feedback system that synchronizes the clock on the circuit with the phase of an external clock

The PLL phase-locked loop has three components:

Phase detector PD, loop filter lf and voltage controlled oscillator VCO

• Principle:

The external input reference signal is used to control the frequency and phase of the internal oscillation signal in the loop.

PD, which detects the phase difference between the input signal and the output signal

LF, the converted voltage is filtered to form a control voltage.

• Frequency multiplier:

Benchmark. N Times harmonics. Lock phase.

External crystal oscillator Clock is the reference!

Voltage-controlled oscillator VCO generates the required frequency!

• Summarized

An oscillating circuit that outputs a certain frequency signal, also known as a phase synchronization loop (loop). The loop uses a constant feedback control that enables the externally applied reference signal to phase with the oscillator output in the PLL loop to produce an oscillating signal.

PLL phase-locked loop for FPGA