Porting ubooot to SDRAM nor flash NAND Flash

I recently started to learn about how to modify lowlevel_init.s. Now I want to transplant uboot by myself. Although I have read some detailed technical information, I am confused about some of the steps, here are two questions to ask.
I am using the mini2440 Development Board, I see a document about lowlevel_init.s modify the following description (using a U-Boot-2008_10)
1.2.3 modify the Board/mini2440/lowlevel_init.s File

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(1) Modify bwscon, The mini2440 bank0 is connected to nor flash, the bank4 is connected to dm9000, And the bank6 is connected to ram. For the mini2440, you only need to modify b4_bwscon:

# Define b3_bwscon (dw16 + wait + ublb)

// # Define b4_bwscon (dw16)

# Define b4_bwscon (dw16 + wait + ublb)

# Define b5_bwscon (dw16)

......

# Define b4_tacs 0x0/* 0clk */

# Define b4_tcos 0x3/* 4clk */

# Define b4_tacc 0x7/* 14clk */

# Define b4_tcoh 0x1/* 1clk */

# Define b4_tah 0x3/* 4clk */

# Define b4_tacp 0x6/* 6clk */

# Define b4_pmc 0x0/* normal */

# Define b5_tacs 0x0/* 0clk */

(2) then modify the refresh cycle:

# Define b7_scan 0x1/* 9bit */

/* Refresh parameter */

# Define refen 0x1/* refresh enable */

# Define trefmd 0x0/* CBR (CAS before RAS)/auto refresh */

# Define TRC 0x3/* 7clk */

# Define TCHR 0x2/* 3clk */

// # Define refcnt 1113/* period = 15.6us, hclk = 60 MHz, (2048 + 1-15.6*60 )*/

# If defined (config_s3c2440)

# Define TRP 0x2/* 4clk */

# Define refcnt 1012

# Else

# Define TRP 0x0/* 2clk */

# Define refcnt 0x4f4/* period = 7.8125us, hclk = 100 MHz, (2048 + 1-7.8125*100 )*/

# Endif

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. Word text_base

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My questions are:
1. From the circuit diagram of mini2440, we can see that bank0 is connected to nor flash, bank4 is connected to dm9000, and bank6 is connected to ram. But why only bank4 is modified when lowlevel_init.s is modified, what about dm9000?
What is the basis for setting these parameters in bank4? Why are these values? For example, # define b4_tacc 0x7/* 14clk */. Why should I set the access period?
For 14 clock cycles, I have read the specifications of dm9000. It seems that I have not talked about these parameters, such as tacc and TCOs. I have not seen these parameters in the detailed sequence diagram? Only in section 5th of the specifications of the S3C2440
The description of bankconn includes the descriptions of these parameters, but which part of the description determines the value?
2. In the same refresh period, what is the basis for parameter settings?
I read a lot of materials and said that I want to modify it here, but I still don't understand why I want to change it like this? Depressed ..

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Today, in order to understand how refresh was set up in the 2nd questions, I read the related sections of the specifications of the S3C2440 and hy57v561620. Found
# If defined (config_s3c2440)

# Define TRP 0x2/* 4clk */

# Define refcnt 1012

# Else
The reason for setting TRP in this section.
In the refresh register of S3C2440, TRP is described as follows:
Trp sdram Ras pre-charge time 00 = 2 clocks 01 = 3 clocks 10 = 4 clocks 11 = Not
Hy57v561620 mentioned this.
RAS/precharge time min 20 NS
In this case, the TRP value should be set as follows:
1. Because the system frequency of mini2440 has been set to 405 m in start. S, a machine cycle is 1/405 M = 2.4ns.
2. The specifications of SDRAM hy57v561620 also tell the minimum value of RAS/precharge time to 20 NS.
3. TRP = 20/2. 4 = 8 clocks (this setting is not available !!)
After a long time, I still didn't see the reason why I set it to # define TRP 0x2/* 4clk */. Did I see it wrong? He set the frequency to MB?

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9/13 again today, we found that the problem was previously ignored. The SDRAM uses hclk instead of fclk.
In start. s, the system frequency of mini2440 has been set to 405 MB and fclk: hclk: pclk =. Therefore, the time here is measured in hclk units.
The hclk has a clock cycle of 1/100 m = 10ns. The specifications of the SDRAM hy57v561620 also tell the minimum value of RAS/precharge time to 20 NS, so we can understand it by taking four clocks here, it only needs to be larger than the minimum value.
There are still doubts about the settings in other places. It does not seem to be able to be solved in the near future. I decided to go back later. Maybe I will have the opportunity to understand why refcnt should be set to 1012 In the case defined by config_s3c2440? How can this value be calculated?

According to the refcnt formula and the refresh cycle 7.8125us of hy57v561620, it should be 0x4f4 (1268 ).

Why 1012 instead of 1268? Refcnt he set here 1012 instead of the 1268 we calculated. I guess later that the author calculated the value at the 133m frequency (you put 133 in the formula as the value he calculated ), instead of 100m.