Post) support for large memory in FreeBSD

Source: Internet
Author: User
Tags intel pentium

Http://www.chinaunix.net Author: Jian Xin transparent published on: 15:01:41
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In the past few days, I have seen a question about the large memory of FreeBSD. I checked the relevant information and summarized it as follows:
1: solution-add options PAE to the kernel
2: Why is this problem?
3: AMD instructions

 

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Jian Xin transparent reply to: 10:34:36

[Color = Red] 1: solution-add options PAE to the kernel [/color]
[Color = Red] the following content is taken from: http://journal.cnfug.org/issue8/41045.html#/color]
Reference:
A large memory machine is a machine with more than 4 GB memory (limited by the sum of user and kernel logical addresses. Is
To solve this problem, Intel Added 36-bit physical address space addressing capability to Pentium Pro and its later CPUs.

The Intel Pentium Pro with the PAE function and its CPU allow a maximum of 64 GB memory. FreeBSD
(4. X series from 4. 9release, 5.x series from 5.1-release) through Kernel configuration parameter PAE
Provides capacity expansion support. Due to the limitations of the annual storage architecture, there is not much difference between more than and less than 4G;
The memory that exceeds 4 GB is only added to the available memory pool.

To add PAE support, add the following line to the Kernel configuration file:

Options PAE

Note: PAE support in FreeBSD is only valid for Intel IA-32 processors. In addition, PAE in FreeBSD
The support has not been extensively tested and should be considered as beta-level like other stable features.

PAE support in FreeBSD has the following limitations:

* The process cannot access memory larger than 4 GB.

* Because of the differences between the building module and the kernel framework, KLD cannot be used in the kernel that uses Pae.

* If you do not use the bus_dma interface device driver, using the kernel supported by PAE may cause data corruption uption,
This type of driver is not recommended. Therefore, in the 5 that supports Pae. X, the kernel rejects all
Unrecognized driver.

* Some system parameters can be used to adjust system memory resources based on the total available memory. PAE is not required for these fine-tuning.
The system memory size is small to allocate. For example, a Kern. maxvnodes sysctl command controls the maximum allowed
Number of vnodes. You need to carefully consider adjusting it and other similar parameters to set it as a reasonable value.

* You may need to increase the virtual address space of the kernel or reduce all serious consumption of kernel resources to avoid KVM failures.
Enough. The Kernel Parameter kva_pages can be used to increase the size of the KVA space.

For performance and stability issues, you can view the tuning man manual. The PAE man manual includes FreeBSD's
PAE supports the latest information.

[Color = Red] handbook Description: [/color]
Reference:
8.4.1 large memory support (PAE)
The machine configured with large memory needs a virtual address larger than 4 GB. Due to the limitations of 4 GB, Intel has added 36-bit physical address support on Pentium & and subsequent CPUs.

Intel & Pentium Pro and subsequent CPUs allow memory address expansion to 64 GB. (PAE) FreeBSD to support this capability through the PAE option. In the FreeBSD 4.x series, 4.9-release is supported. In the FreeBSD 5.x series, 5.1-release is supported. In the 4.x series of FreeBSD begbeginning with 4.9-release and in the 5.x series of FreeBSD beginning with 5.1-release. Because of Intel architecture restrictions, there is no difference between the above or below 4 GB, the memory allocated to more than 4 GB only increases the available memory pool.

To make the Kernel support PAE, add the following line to the configuration file:

Options PAE
Note: PAE now supports only intel IA-32 processors in FreeBSD. At the same time, it should be noted that FreeBSD's PAE support has not been extensively tested and can only be considered as a beta version compared to other stable features.

PAE has the following restrictions in FreeBSD:

Processes cannot access VM space larger than 4 GB.

THE KlD module cannot be loaded into a kernel that has enabled the PAE support, because the kernel module and the kernel build framework are different.

A device driver that does not use the bus_dma (9) interface opens the kernel supported by PAE, causing data corruption ). For this reason, the PAE Kernel configuration file of FreeBSD 5.x excludes all drivers that cannot work on the kernel with the PAE enabled.

Some systems enable the probe system memory resource usage function, because the PAE support is enabled, these functions may be overwritten. One example is the Kernel Parameter Kern. maxvnodes, which controls the maximum number of vnodes used by nuclear energy in the system. We recommend that you re-adjust it and other similar parameters to the appropriate value.

To avoid kVA consumption, it is necessary to increase the system kernel virtual address or reduce the total number of kernel options that consume a lot of system resources (see the above ). The kva_pages option can be used to increase the KVA space.

To ensure stability and high performance, we recommend that you view the tuning (7) manual page. The PAE (4) manual page contains the latest information supported by FreeBSD 'spae.
I found it on lists.freebsd.org. Even the English language is poor. Which of the following is the translation of the eldest brother :)
Reference:
First thing to keep in mind is that I'm talking about physical
Addresses, not OS-specific virtual addresses. Second thing to keep in
Mind is that I'm talking about * address space *, not * Ram *. There is
Big different here. An address represents a location where data can be
Stored or retrieved. That location does _ not _ have to be Ram. It cocould
Be a register on a APIC chip, or a memory array on a PCI Card, or
Location in a local RAM chip.

PCI (AGP is really just like PCI from this perspective) specifically
Allows the CPU to access registers and memory arrays on the cards as if
They were local addresses, that's the point of the memio registers and
Base address registers. When the CPU does a load or store of an address
That falls into these address ranges, the request doesn't go to ram, it
Goes to the PCI bus and is serviced by the appropriate card there.
Local Ram doesn' t get involved at all.

PCI doesn' t actually care much which addresses are used, but
Convention the PC platform puts them at the top of the 32-bit address
Space. But, what happens when you have so much ram that the ram cocould
Service those very high addresses? For policyears that wasn' t an issue
Because it wasn' t possible or practical to put that much ram into a PC.
But now it is, so it's up to the memory controller and host bridge
Figure out what to do. Wait systems cause that high Ram to simply be
Ignored, resulting in the loss of dynamic RAM (as you saw in your
Case). More complex systems will take the ram that wowould occupy that
3.5-4 GB address space and re-map it into the 4.0-4.5 address space.
Ram doesn't care because it's just an array of storage cells, it's up
The memory controller to associate addresses with those storage cells.
Of course, that only works if you're using a 64-bit (or 32bit PAE
Enabled) OS that can deal with physical addresses larger than 32 bits.

Intel Xeon systems typically do the remapping trick, so when you boot
FreeBSD i386 + PAE or amd64 on them, they might show 4.5 GB of ram when
There reall is only 4 GB (this is a limitation of how we compute Ram and
Is purely cosmetic, but shocould be fixed). AMD opteron systems do
Not do the remapping and result in you loosing valid Ram.
Difference between Intel and AMD is because amd puts the memory
Controller Into the CPU instead of in the PCI host bridge, so it's much
Harder to have the two work together to do the remapping. I believe
That there are some opteron systems that can do this, though.
3.5.8 memory Hoisting
Typically, memory mapped I/O space is mapped from mmiolowaddr to 4gb-1, and DRAM
Memory is mapped from address 0 to top_mem, an address that is less or equal to mmiolowaddr-
1. DRAM memory can also be mapped from 4 GB to tom2, an address greater than 4 GB. Memory
Hoisting is defined as reclaiming the dram space that wocould naturally reside in the mmio hole just
Below the 4G address level.
3.5.8.1 memory Hoisting for revision D and earlier revisions
Depending on the mmiolowaddr value and how DRAM is populated, DRAM base and limit
Registers and dram cs base and limit registers need to be programmed differently. If possible,
Contiguous memory mapping is used. Sometimes a memory hole is generated in the DRAM Memory
Map (node hoisting) or in the dram CS map (chip select hoisting). In the case of chip select
Hoisting, the memory hole is wrongly ded in the memory map for the node that has a hoisted chip select.
The memory hole generated by the BIOS is equal to or greater than 4gb-mmiolowaddr.
Chip select hoisting can not be used in the case of a single 4 GB chip select bank. Also, DRAM and
Node memory interleaving can not be used on a node with chip select hoisting.
Mmiolowaddr is not known by the BIOS at the time when dram chip selects are programmed in
Post. The bios either assumes the mmiolowaddr value or uses the value selected by the user
With a setup option.
The following algorithm is designed to be used to generate the DRAM Memory Map and DRAM CS
Map. top_mem is MSR c000000001ah, tom2 is c000000001dh, max_nodes is number of nodes
100 Memory System Configuration chapter 3
26094 rev. 3.26 unzip l 2005 bios and kernel developer's guide for the amd athlon & #8482; 64 and
AMD opteron & #8482; Processors
In the system, nodebase are DRAM base registers, csbase are dram cs base registers,
Csmask are dram cs mask registers, be are csbe bits in dram cs base registers.
Top_mem = tom2 = memtop = 0;
For (node = 0; node <max_nodes; node ++ ){
Nextcsbase = 0;
Nodebase [node] = memtop;
For (P = 0; P <8; P ++ ){
Maxbanksize =-1;
For (q = 0; q <8; q ++ ){
If (size [Q]! = 0 & be [Q] = 0 & size [Q]>; maxbanksize ){
Maxbanksize = size [Q];
B = Q;
}
}
If (maxbanksize! =-1 ){
If (memtop & memtop <4 GB & (memtop + size)>; mmiolowaddr ){
Top_mem = memtop;
Memtop = 4 GB;
If (nodebase [node] = top_mem) {// node Hoisting
Nodebase [node] = 4 GB;
Nextcsbase = 0;
}
Else {// chip select Hoisting
Csbase = 4 GB-nodebase [node];
Nextcsbase = 4 GB-nodebase [node];
}
Else {
Csbase = nextcsbase;
}
Memtop = memtop + size;
Csmask = size-1;
Nextcsbase = nextcsbase + size;
Be = 1;
}
}
}
If (top_mem) tom2 = memtop;
Else top_mem = memtop;
3.5.8.2 memory Hoisting for Revision E and later revisions
Memory that resides in the mmio is repositioned above the 4G level by programming the dram
Hole address register and the dramlimit properly. For systems that have node interleaving Enabled
These registers must be programmed on all nodes, otherwise only the node with the dram hole needs
To have these registers programmed.
The memory hoisting offset field, dramholeoffset, is programmed as shown in the following
Equation:
Dramholeoffset [31] = (100 h-dramholebase [31]) + drambase [31]);
Chapter 3 Memory System Configuration 101
Bios and kernel developer's guide for the amd athlon & #8482; 64 and
AMD opteron & #8482; Processors
26094 rev. 3.26 limit l 2005
The dramlimit field must be programmed to include the size of the dram hole as shown in
Following equation:
Dramlimit = 4 GB + hole size;
Example. A two processor system with 4 GB dram on each processor and a 1 GB mmio hole.
Processsor 0 drambase [39] = 0000 h.
Processor 0 dramlimit [39] = 013fh (5 GB-1)
Processor 0 dramholebase [31] = c0h (3 GB ).
Processor 0 dramholeoffset [31] = 40 h (1 GB ).
Processor 1 drambase [39] = 0140 H (5 Gb)
Processor 1 dramlimit [39] = 023fh (9 GB-1)
Processor 1 dramholebase [31] = 00 H (memory hoisting is not enabled on node 1 ).
Processor 1 dramholeoffset [31] = 00b (memory hoisting is not enabled on node 1 ).

 

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