PowerPC VxWorks BSP analysis (3.1) -- powerquicc hardware

1 powerquicc hardware 1.1 MPC860 memory interface

The MPC860 Storage Management provides 8 memory chip selection signals that can be seamlessly connected to SRAM, EPROM, flashrom, SDRAM, edoram, and other memory devices. The memory access is implemented through the corresponding registers and time series Ram provided by the MPC860 to control the time series of the corresponding interface signal.

The interfaces between the MPC860 and external memory are as follows:

① Data Bus [0: 31], 32-bit;

② Address of the address bus [0: 31], 32-bit;

③ Control bus chip selection/CSO-/cs7, read/write r/W, general control line GPL-x0 ~ GPL-x5, byte switching/BS [0-3], burst indication/burst, calibration acceptance indication DP [0-3], bus shared signal/BS,/BR, /BG,.

The interfaces between the MPC860 and external memory are divided into two types by storage method: gpcm (General chip selection mechanism) and UPM (User Programming Mechanism ). The address bus and data bus are the public parts of the control bus, including the slice signal line (CSX), R/W, BS-ax, GPL-X, and DPX.

(1) gpcm (general-purpose chip-select machine)

Gpcm provides an access method for low-speed and low-efficiency storage chips. It does not provide a burst access mechanism, therefore, this mechanism is usually used for system boot chips and access to non-burst chips. The width of the Data Bus can be 8-bit, 16-bit, and 32-bit. The Flash ROM described below uses the 8-bit data bus.

(2) upmx (User-programmable machines)

The User Programming Mechanism supports external address arbitration, periodic clock, and generation of row and column timing that truly connects to DRAM devices seamlessly. This mechanism can generate different time sequences to satisfy read, write, burst read, burst write and other operations. This mode supports a 32-bit data bus.

The following table lists the registers that the MPC860 registers for storage control. All registers are 32-bit wide.

· Brx and BR and or are used in pairs with the same subject matter as orx. brx defines the starting address (16-bit high) and access method (gpcm or upmx) of the selected block), read/write protection method, and check whether or not. Orx defines all parameters of the corresponding Address Mask (16-bit high) and gpcm mode.

Note that br0 and or0 are different from other brx and orx. The value in br0 is related to the power-on configuration word designed on the bus during system initialization. The gpcm parameter in or0 is fixed and read-only, these features determine that the memory on CS0 can only be a system bootrom and the hardware design sequence adopts the gpcm mode.

· Mstat reports external memory verification errors and write protection errors.

· MCR reads and writes the content of the UPM-RAM during UPM Mode Initialization. Of course, you can also use it to simulate the UPM mode, so that the CPU can not only complete the standard memory read/write and cycle timing, but also complete the operation of specific memory. For example, the operation on SDRAM.

· MCM stores the content to be written or read from upmram. Therefore, data must be set in advance before executing the MCR write command.

· Configuration registers of mamr, mbmr: upma and upmb. Including address arbitration and various periodic orders. Among them, 16-18 bits goclx [0 .. 2] indicates that when Gol and Goh In the Memory RAM word are fully enabled in the UPM mode, the address line definition of the output to/gplo is selected (with the design of SDRAM, 010, output A10 to/gplo ).

And flashInterface:

Compared with the UPM mechanism, the gpcm of the MPC860 is much simpler in terms of both hardware interface and software register programming settings. The time sequence of gpcm access to memory and the interface design is the same as that of General processor interfaces, it is easier to understand. For gpcm, there are only three registers used: brx, orx, and mstat. We only need to correctly set the programmable part in br0 and or0 for flash memory, and design the reset configuration word on the bus according to the parameters. This sst39lf016 is 2 Mbyte, 8-bit data width, addressing is 0x12800000, so br0: 0x12800401, or0: 0xffe0920, its reset configuration word design.

When the system is reset, The hreset is opened with 2 low chips 244, And the MPC860 is read into the bus with 16 low bits, which corresponds to the following table configuration characters. BPS (d4d5) is the bus width at the beginning.

And SDRAMInterface (internal address arbitration ):

We can see that the signal generation between the MPC860 and the memory interface is achieved through correct settings of 64 32-bit Ram word programming and chip selection registers (brx and orx. Ram programming is complicated and cumbersome. You can use tools and software to generate required data as needed.

At present, the market performance is better than the good memory, there are 168 lines of edoram and 14.4 lines of SDRAM notebook memory, in this design we use 144 line of SDRAM. The gpl2 output line selection signal (/RAS) of the MPC860, The gpl3 output Column Selection signal (/CAS), and The MPC860 address line (A18-A29) are reused when using the internal arbitration logic, high-end address line A9 A20 as the line address in the Ras effective reuse in A18,/gplo, A20-A29, this multiplexing relationship is set by AMX (001) in mxmr, of course, the setting for memory with different row and column values is different. The reuse or not is determined by the orx [Sam] bit (0 is not reused, 1 is reused) and the memory word [AMX] bit. Here, we note that A19 is replaced by/gplo. During address arbitration,/gplo is determined by the goclx [0 .. 2] bit of mxmr to determine the sequence of the address line to be executed. In this design, the memory size is 64 MB and 12 rows and 9 columns. The interface connection is shown in the figure below. Select cs5 for slice selection, and set the memory base address to 0x00000000. The settings are as follows:

Or5 = 0x00000a00 (Sam = 1 Internal Arbitration, BiH = 0 support for burst (burst) mode), br5 = 0x00000081 (MS = 10 upma mode, PS = 00 32-bit, mamr = 0x9c924111 (AMX = 001, A9-A20 reused to A18-A29, gociac [0 .. 2] = 010 A10-& gt; gpl0 ).

And SDRAMInterface (external address arbitration ):

External address arbitration uses the gpl5 pin provided by the MPC860 to select external arbitration addresses outside the MPC860. In this case, the address lines of the MPC860 are not reused, instead, 21 IP address lines in 12 rows and 9 columns are connected to the and B ends of the 74ls257 device, respectively, and 12 IP address signals are selected during the row lock cycle, in the column lock cycle, nine column address signals are selected, which is the function of gpl5. Other signals are the same as internal address arbitration.