Principle and application of single chip network interface chip W5100

　　With the development of computer network technology, as the world's largest computer network, i n T e r ac T has become an important basic information infrastructure in today's information society. In the field of industrial measurement and control, intelligent instrument, intelligent home and so on, a large number of applications embedded equipment i n T e R n e t requirements make embedded i n T E R-AC t technology is becoming a hot topic in research. The key of the embedded device i n T e R n E T is how to implement the T C p/i P protocol cluster in the embedded device with limited hardware resources. Implementing complex T-C p/i p protocols consumes a large number of important resources, which will inevitably affect the nature of embedded devices Increase the complexity and cost of system design. Wl Z n e T launched a series of hardware stack chip--W5 1 0 0 network interface chip--for embedded device access I N T e R n E t provides a good solution. This kind of network interface chip can enable the embedded device to complete the network communication quickly under the condition of occupying very low system resources. WI z N e T is a fabless semiconductor company that specializes in all-hard wiring T C p/i P Core technology. Currently, WI Z n e t company launched a series of hardware stack chips have W3 I o o a-l F, W3 1 5 0 A, W3 1 5 0 A + , W5 1 0 0,w5 3 0 0. Wherein, W5 1 0 0 is an upgraded version of W3 1 5 0 A, which adds an Ethernet P H Y on the basis of W3 1 5 A, which is implemented using logical hardware to make the system design simpler and more compact. W5 1 0 0 is a multi-functional monolithic network interface chip, which is mainly used in embedded systems with high integration, high stability, high performance and low cost. This paper mainly introduces the internal structure, working principle and application design of W5 1 0 0 chip, and lists a practical example.

1, W5100 Chip introduction

Since W3 1 5 0 A requires an Ethernet physical Layer interface Device (R T L 8 2 0 1 C P) to be used outside, the hardware difficulty ¨ is increased when used, so Wl Z N e T company recently launched the W5 1 0 0, which is based on W3 1 5 0 A +, integrated The Ethernet physical layer R T L 8 2 0 1 C P-Core, the T C p/i p protocol stack, Ethernet M A C and P H y 3 functions are integrated. W5 1 0 0 not only retains the original parallel bus interface with the MC U interface, but also adds the S P I serial Bus interface. W5 1 0 0 1 0/1 0 0 Mb P S Ethernet ma C and P H y are integrated into automatic M D I X, with 1 6 k B data buffers, line transfer rates up to 2 5 Mb P S. In addition, its biggest feature is in addition to support T C p, A R p, I C M p and other hardware stacks, but also support P p p O e protocol, do not need to go through A computer directly to pick up a D S L, to achieve data communication. W5 1 0 0 can be used where high communication rates are required, such as set-top boxes, digital video recorders, Ethernet networks, remote controllers, etc. W5 1 0 0 "3-in-1" function can meet a variety of microcontroller without operating system support to pick up I N T e r ac T, and simple, reliable, inexpensive, has been widely used in various security monitoring, audio and video transmission, remote information transmission and other fields.

1.1 chip pin distribution and function

The W5100 pin distribution is shown in 1.

The W5100 has 80 pins in a LQ FP package, which can be divided into the following 6 classes according to the function.

1.1.1 MC u connector type pin

There are 33 types of pins on the microprocessor interface, including 4.

(1) Address bus pin (1 5) A D D r[1 4~0] corresponds to 3 8-42 and 45-54 pins, which are used to select registers or memory. These address bus are used when the bus-based communication between the W5100 and the MCU is used.

(2) Data bus pin (8) D a T a[7~0] corresponds to the pin l9~26, which are used to read and write to the W5100.

(3) Control bus pin (5)/R e S e T is 59 feet, as a pin to initialize the W5100 chip, the low level is active; CS is 55 feet, as a pin for chip selection on the W5100 chip, the low level is active; I N T is 5 6 feet, is the interrupt output pin, when the W5 1 0 0 Internal interrupt occurs, the PIN output low level; The wr,/R D is 5 7 and 5 8 pins and is a read-write control signal that is signaled by MC u when reading and writing data to W5 1 0 0.

(4) s P I interface pin (5) s E n is 3 o feet, s p I interface enable PIN, so that pin is low, then S p I mode is forbidden, otherwise valid; S C L K for 2 9 feet, s P I clock input; s C s for 2 8 feet, s P i from mode selection, low active; MO s I for 2 7 feet, S P I main out from the human data line pin; MI S O is 2 6 feet, the master from the data line pin.

1.1.2 Ethernet Physical Layer Pins

A total of 8 pins, including the following 4 kinds.

(1) input differential signal line pair pin (2) R X I p is 5 feet, is the positive pin of the signal line pair; R X I N is 6 feet, which is the negative pin of the signal line pair.

(2) The output differential signal line pair pin (2) R X O is 8 feet, is the positive pin of the signal line pair; R XO N is 9 feet and is the negative pin of the signal line pair.

(3) Operation control mode pin (3) O P MO D E [2-0] is 6 5-6 3 pin, to 3 pin different signals, the Ethernet physical layer will work in different modes. For example: 0 0 0 for automatic handshake, 0 0 1 for 1 0 0 B A S e-t X F D S/HD x automatic handshake, etc., see reference [1] for the remaining patterns.

(4) Other (1) R S E t-b g is 1 feet, the pin needs to add a 1 2 to the ground. 3 k Q, the resistance of error 1%.

1.1.3 Clock Signal pin

The X t L p is 7 6 feet and X t l n is 7 5 feet, which is used for external crystal oscillator of 2 5MHz.

1.1.4 working status L E D lamp signal pin

Working status L E D lamp signal pin total 6. W5 1 0 0 Chip 6 6, 6 7, 7 o~7 3 pin output connection, connection speed, duplex mode, I p address conflict, receive, and send status signal, respectively connected to an L E D lamp display, low active.

1.1.5 Power Pin

The W5 1 0 0 chip has 3.3 V and 1.8 v two operating voltages, of which 1.8V is generated internally by the chip and 3.3V power supply is provided by an external circuit.

1.1.6 Other Pins

(1) Mode selection pin (4) T E S t-m O D e[3~0] is 3 4~3 7 total 4 pins, W5 1 0 0 mode selection, 0 0 0 0 for General mode, others for internal testing.

(2) N C pins (7) are mainly 3, 6 0~6 2, 7 8~8 o a total of 7 pins for manufacturers to test.

1.2 W5 1 0 0 internal structure

The internal structure of the W5 1 0 0 is shown in 2. Its chip is mainly composed of 4 parts, namely: Hardware T C p/i P Core, Microcontroller MC u interface Unit, send/Receive data buffer, Ethernet physical layer unit.

W5 1 0 0 contains a public register, a port register, a send and receive data buffer, and a memory address space of 3 2 K B. Wherein, o x o 0 0 0~o x 0 0 2 F Unit is a public register, o x 0 4 0 1 O x 0 7 F F unit is Port Register, O X 4 0 0 1 O x 5 F F F Unit is transmit memory, O x 6 0 0 1 o x 7 F F F unit is receive memory and the remainder is reserved area.

1.2.1 Public Register

The public registers mainly include the mode register (M R), Gateway address register (G WR), Subnet mask register (s U B R), native hardware address register (s H A R), native I p address register (s I p R), interrupt register (i R), Interrupt mask Register (I MR), Retry time Register (r T r), Retry register (R C R), receive data buffer size register (r ms R), and send data buffer size register (T ms R), etc.

(1) The local configuration register includes s I p R, s U B R, S H A R, G WR and other 4 registers, mainly used for storing this machine's I P address, subnet mask, hardware address, and gateway I p.ws 1 0 0 before communication, these registers must be configured beforehand.

(2) Interrupt related registers include I r and I Mr Registers. I R's D. In ~d, 7 bits, except for D, are 7 interrupt source flag bits W5 1 0 0 respectively.

D 0-d 3 is the interrupt flag bit for the 4 ports of W5 1 0 0, and the position is generated when an interrupt occurs on the S o C K e T. The 5th digit shows whether the p p p O connection ends, and if it ends, the location is 1; the 6th bit is the display bit for which the target is not connected; 5, 6, 7 bits can be automatically cleared by the bit write "1" 0. Any interrupt bit can be masked by the bit in I Mr.

(3) The data Buffer settings register includes R M S R and T MS R Registers, the main setting is the size of the receive/send data buffer. The receive/Send data buffers are 8 K in total, and the buffer size of 4 channels can be flexibly allocated by setting R MS R and T Ms R.

1.2.2 Port Register

The port register is mainly used to control the data receiving and transmitting of each channel after network connection. W5 1 0 0 supports 4 paths, and corresponds to a fully equivalent 4 socket register, i.e. SN =s0, S1, S2, S3. Channels have a separate set of registers.

(1) The Port command Register (Sn _ C R) is mainly used to control the initialization of the corresponding port, shutdown, and establish connection and termination, data transmission, command reception. A different control can be achieved by writing the corresponding value to the bit.

(2) The Port interrupt register (Sn_i R) is mainly used to communicate the connection situation, the d0-d4 of Sn_ I R respectively corresponds to the operation status of connection, disconnection, receiving, time-out, sending success, etc.

(3) The Port status register (sn_s R) is used to display the various conditions of the corresponding port. For example, set sn_s R initial state is sock-c l O s e D when the command register is placed as L I S T e N, and S O C K E T (n) is placed as T C P Server mode and the connection is established normally. At this time, Sn_ s r= s O C K-L I s T E N; When the command register is set to O p E N and the mode is U D p, sn_s r=s O C k-udp.

2 W5 1 0 0 Application Example

2.1 Single Chip microcomputer and W5 1 0 0 interface Design

In this paper, a T 8 9 S 5 1 MCU is a microcontroller, briefly introduces the application design of W5 1 0 0 chip. The bus interface method is adopted to improve the data transmission rate and to facilitate the interface. The bus interface mode needs SCM to provide more I/O lines, but the connection method is simple, only need W5 1 0 0 chip address total The line, data bus and control bus correspond to the corresponding bus of the microcontroller A T 8 9 S 5 1.

Figure 3 is a peripheral connection circuit for the W5 1 0 0 chip. Figure 4 is a T 8 9 S 5 1 Microcontroller control circuit. Address bus for A15 ~0, where A14 ~a0 connection W5 1 0 0 chip address bus a14~ A 0, A15 connection W5 1 0 0 chip/C S feet . Therefore, the address of the W5 1 0 0 chip is 0 0 0 0 h~ 7 f F f H. The microcontroller can easily access all registers within the W5 1 0 0 chip through its bus structure. Since the W5 1 0 0 chip incorporates an Ethernet physical layer unit, the W3 1 0 0 A core can be omitted Chip application circuit such as R T L 8 2 0 Ethernet Physical layer chip, to simplify the circuit, save costs, improve the reliability of the circuit.

2.2 W5 1 0 0 Communication programming

To use the W5 1 0 0 module to achieve data transmission in the Internet, the need to write a single-chip computer control program. A T 8 9 $5 1 microcontroller program can be used in assembly language or C. The main processing procedure for C language is as follows.

(1) Initialize i n i t W5 1 0 0 A 0//initialize W5 1 0 0, set the size of each receive/send data buffer; s e t g a t e w A y (i P)//set gateway; S e T M a C a D d r (I p)//set physical address; S e t s u b ma s t (i p)//set subnet mask; S e t L p (i p)//set L P address; S e T r C R (t i m e)//set timeout time; i n i-t-S o C K (i, I P o r T, f l A G, 0, sn_mr_t C p)//initialize each socket.

(2) Connect s o C K e T (I, S one Mr _ T C P, L o c a l-P o r t +l N c+ +, 0)//set T C P mode, C l e N T port; c o n n e c t (i, I p, p o r T)//Connect the server with the I p and port set.

(3) Data transmit and transmit r e C V (i, R x-b u F, l e N)//s o C K e T (i) receive l e n length data, stored in I x-b u f; S e n D (i, T x-b u F, l e N)//S o C K e t (i) send l e n length data via T x-b u F.

3. Conclusion

W5 1 0 0 chip launch, greatly simplifies the hardware circuit design, so that the SCM system without operating system support, really make a single-chip pick I N T e r ac T become a reality. W5 L O 0 on the basis of the previous network interface chip, the T C p/i P protocol stack, Ethernet MA C and P H y are integrated on a chip, which greatly simplifies the difficulty of hardware design. Moreover, by embedding the hardware protocol stack internally, the traditional cumbersome Ethernet protocol writing and debugging steps are eliminated, and the system development speed is accelerated, so the core The application of the film has good prospects. W5100 Sample Application Http://www.xhl.com.cn/ylogin/w5500.asp!

Principle and application of single chip network interface chip W5100