Problems encountered in pads-emsym angxin Technology

Original Title: problems encountered in powerpcb Reprinted from: http://www.emsym.com/blog/ Emsym angxin Technology

1. Questions about the virtual outer frame of the passing hole:

As shown in:

The outer frame refers to the gap between the via and other devices. The size can be set in design rule. The size of the isolation ring between the copper skin and the hole is the distance between the hole and the copper skin (via to copper). By setting the distance, determine which holes need to be connected to the copper skin, which must be isolated. The distance between the connected hole and the copper skin is set to 0. The effect is as follows:

 

2. Introduction to pads middle-level types:

All plane layers include non-special layers (non-flat layer no plane, usually the Strip routing layer) and special layers (including the cam plane layer and split mixed layer ).

A. No plane: usually refers to the Strip layer, such as top bottom, and the middle strip layer, which is output as a main part.

B. cam plane: It is output in the form of a negative slice. Layer Separation is implemented in 2D line without Copper laying. It is usually used in power supply layer and formation, and the amount of data occupied is much smaller, however, there is a drawback that the design rules will not be checked, that is, the network allocated to this layer will not be checked for security spacing and connectivity. Therefore, the split layer must be self-guaranteed. If you set the power supply and ground to the cam flat layer, the gerber file is output as a negative slice. at this time, the network in the current layer will automatically generate flower holes and do not need to connect them through wide wires or copper. then, when we get the PCB Board factory, we will replace the whole network with copper, and it is already a form to leave copper in the design of the Board. of course, if you set it to no
Plane must be paved. The step is to draw a copper area, set the network in this area to power or Gnd, and then flood all!

C. split/mixed plane: mixed layer, output in the form of positive slices, copper needs to be paved, but the copper is different from no plane, you can choose to split the block by block shop, the unified operation is performed on the plane CONNECT page of tool/pour manager. This layer checks the rules during rule validation. Splitting the mixing layer split is also used to process power supply or Gnd, but it is the output positive, so the power And Gnd assigned to this layer must be connected by copper, the system automatically splits two parts without any connection relationships. You can also wire them at this layer. we do not recommend this setting.

When mixed plane is used as the power layer or formation layer, the layer separation process may cause a layer of copper to be completely surrounded by another copper, or overlap, after pour operation, in this case, the priority level (flood priority) of the shard needs to be set. The lower the level, the higher the priority, the higher the copper, that is, the overlapping part is classified as the lower-priority part.

3. Differences between hatch and flood are as follows:
We know that the boundary of the copper-clad area in powerpcb is composed of an arc and a line. This boundary describes the range of copper-clad areas. Flood covers copper according to existing design rules. The software recalculates and determines the boundary of the copper-clad area according to the design rules. Hatch is simply copper-coated in the copper-covered area boundary of the existing copper-covered area, or simply understood as "Visualization of copper-coated areas", this operation is often required to open a copper-coated board.

In terms of image, flood is literally the meaning of a flood. When the water flows over, everything must be updated, and all boundaries must be redefined. Of course, a natural flood must follow the natural law, copper-coated flood will follow the design rules. Hatch, literally, refers to hatching. hatching means growing up in a shell. This "shell" is the boundary of the copper-covered area, where copper is... Grow up until it is filled.

Sometimes, we will make a relatively large design, this is a large file, and the operation time is also very long, so if there is a misoperation, it is likely to destroy the powerpcb database, it is often forced to close the design or cause synchronization failure or even failure to output *. ASC file. Therefore, it is best to give you a lead when your design time is relatively long *. ASC file, and then import this file to generate a new *. the PCB database can be organized once to avoid errors mentioned above. When you change the board, we recommend that you do this first, saving you a lot of trouble!

4. When powerpcb Gerber is out *. Rep, *. Pho, *. DRL, *. lst each indicate what they mean, and which files are required by the PCB manufacturer when making a board?
*. Pho Gerber Data File
*. Rep D code file (wire, Pad Size, essential)
*. DRL drilling File
*. Coordinates of various lst Holes
The above files are all required by the PCB manufacturer.

5. What is the use of the 25-layer powerpcb?
The 25-layer storage of powerpcb is power supply and ground information. If the multi-layer board is used, setting it to Cam plane requires 25 layers of content. When setting the pad, layer 25 is 20 mil larger than other layers. If it is a positioning hole, it is larger.

6. Solution to the Problem of wiring deprecated after pads router moves the components:

Open the tools-> options-> placement tab and select during move or after move in the reroute traces box. Do not select no rerouting.

7. The problem of drawing through holes or pad in the device encapsulation:

Some plug-in element encapsulation requires pad stack. Besides the default three layers: mounted side, inner layers, and opposite side, Pad Size and aperture must be set, you also need to add layer 25.

Open the through-hole pad stack, as shown in:

Click "add" to add a new layer. Select "layer_25" in "layer selection". Set "layer 25th" to "Pad Size: 20mil or 0.6mm larger than other layers, with the same aperture.

If no layer 25th attribute is added to the pass hole, the hole in the PCB is connected to the copper foil on the grounding plane, and there is no isolation ring around the hole. The data on the second layer is about the electrical properties of the ground plane. It is generally used when the ground plane is set to Cam plane.

8. Batch drilling of BGA pins:

BGA pins are several hundred. If you punch one by one, it is not only time-consuming and labor-consuming, but also difficult to align, and the gap between the hole and the pad is not easy to control. You can use the fan-out function of the pads router to automatically punch holes.

Select the BGA device and right-click Properties, as shown in:

In via biasing, select an appropriate hole, select an appropriate strip width in routing, set clearance properly, and then Perform Batch drilling. After setting the rules, select the BGA device, right-click the fanout option, and then fine-tune it.

9. The grid is generally set to 20mil during component layout.

10. Principle of minimizing noise in System Interconnection:

1. Strict signal networks must be deployed on the same signal layer, and the wires should be kept as short as possible. Therefore, the layout layer of the signal network should be avoided. Inter-layer signal transmission will cause reflection and reduce the line impedance.
2. Is the path of the adjacent signal layer to each other into a right angle (vertical ).
3. Each signal layer is isolated from each other through the ground layer or power layer.
4. The layout of parallel signal lines should be as close as possible.
5. The length of the differential wire pair must be consistent.
6. Minimize the size of the through hole.
7. Try to use the same strip width for strip.
8. Use the widest possible route to reduce the DC resistance.

12. Placement of decoupling capacitors:

The power supply end of the decoupling capacitor shares the same pad with the power supply pin of the IC, minimizing the gap between the IC and the decoupling capacitor. The ov plane should be set to directly adjacent layers on the PCB Surface Layer where components are installed, and all components should be connected to him using the shortest and shortest lines, that is, using direct recent grounding.

If for some reason, the decoupling capacitor must be moved to the principle IC power supply pin and cannot be used for the same pad, it is best to use a small area copper surface (a small area of the power supply plane) between the IC and the decoupling capacitor to replace the line, so as to minimize the interconnect inductance of the decoupling capacitor.

Layout of parallel decoupling capacitors:

Using several parallel decoupling capacitors is one way to reduce their ESL impact. However, to reduce the effect of ESL, the effect of ESL is obvious only when the mutual connection inductance of the decoupling capacitor is much smaller than that of the ESL of a single decoupling capacitor. This is because it is difficult to allow an extra decoupling capacitor to use the same pad as a power pin of the IC. Therefore, the layout of a small area power supply plane is often used.

Generally, when n decoupling capacitors are used in parallel, the total impedance is reduced. Although their parallel impedance is theoretically 1/N multiplied by the impedance of a single decoupling capacitor, in practice, the degree of reduction depends on the layout of each other, only when the layout is reasonable can the obtained impedance be 1/10 of the impedance of a single decoupling capacitor.

The most explicit way to design multiple decoupling capacitor la S is to arrange them one by one in a row and design all 0 V connections at the same end. However, such a layout will not produce the required impedance reduction effect. This is not only because their current flow is in the same flow direction, but also because the close between devices forms a considerable mutual inductance. Therefore, the overall effect of impedance reduction caused by such a layout will not reach 1/10. Therefore, when such a layout is used, the gap between devices is usually opened to minimize mutual inductance and minimize the overall impedance.

However, if the device can be set to offset the magnetic flux formed by the current flowing through them, the device can be placed together. Such as placement: (Dell patent: 6337798)

An example of this placement method is the case where several decoupling capacitors are needed on some power supply pins of the BGA-encapsulated CPU.

The placement method of is unable to achieve the effect of parallel decoupling:

 

The decoupling capacitor placement is as follows:

Note the following in PCB.

13. 20 h rules:

20 h is used to ensure that the edge of the power supply plane is reduced at least 20 times the layer distance between two planes than that of the 0 V plane. This rule is often required to be used as a side-side shooting technique to reduce the plane structure from 0 V/power.

However, 20 h rules only provide obvious results under certain conditions. These specific conditions include:

(1) The rise/fall time of current fluctuation in the power supply bus must be less than 1ns.

(2) The power supply plane must be on the internal layer of the PCB, and the upper and lower layers adjacent to the PCB must be 0 V. The distance between the two 0 V planes is at least 20 times that of the layer between them and the power plane.

(3) The power bus structure will not produce resonance at any frequency of interest.

(4) The total number of PCB layers should be at least eight or more layers.

14. Questions about solder protection disks on the ground plane:

On the ground plane, the existence of any gaps and holes is harmful to EMC, because they will inevitably increase the impedance and prevent the RF Return Current from flowing freely. Because there must be a clearance hole (Solder Mask) around each through hole, the solder mask should be designed as small as possible to improve EMC performance without seriously affecting product output. In addition, do not rely too close between Solder Pad, try to avoid the occurrence of Solder Pad cross together, this will seriously affect the current loop. Pay special attention to the layout drilling.

15. Design Rules priority sorting:

Component> decal> pin pair> group> net> class> default

16. Before exporting the gerber file to the PCB, add the dimension labels to the outer frame of the board and add them to layout directly. Then, the layout is automatically output to the drill drawing layer.

 

The above problems are some of the problems and solutions I encountered during the use of padslayout and router. I hope they will be useful to you. Please also discover and add more questions! Thank you!