Programmer must know the delay time

L1 Cache 0.5ns

Transfer, branch prediction 5ns

L2 Cache 7ns 14 times times L1 Cache

Lock \ Unlock 25ns

Access memory 100ns 20 times times L2 cache, 200 times times L1 Cache

1 K-byte compression (Zippy) 3ns

Send 1k bytes 10us on the precursor NIC

SSD Random Read 4K data 150us

Read 1MB data from memory sequence 250US

Same data center round trip 500US

SSD sequential read 1MB data 1ms 4 times times Memory

Mechanical disk seek 10ms 20 times times transfer data in the same data center

Mechanical disk sequential read 1MB 20ms 80 times x memory, 20 times times SSD

https://gist.github.com/jboner/2841832

Programmer must know the delay time