PTPX Power Analysis Flow

The PrimeTime PX tool is a feature within the PrimeTime tool.

The power analysis of the PTPX can report the power dissipation at each level of the Chip,block,cell.

Use PTPX to analyze the way power is used:

1) Average power Analysis, which supports the propagation approach to activity, is primarily used to evaluate early in the project.

Can be a defaults,user_defined,derived from HDL simulation switching file.

2) time-based power analysis, using the event-drived algorithm to calculate power consumption.

Mainly used in the project Signoff time, add ir-drop analysis.

Power consumption in the circuit:

1) leakage power, the power consumption of the circuit at inactive or static.

Intrinsic leakage power, mainly source-to-drain subthreshold leakage.

The current leak between diffusion layers and substrate.

This leakage is state and voltage dependent.

The main source of gate leakage Power,leakage is the Power of source to gate and gate to drain.

Mainly by gate oxide thickness and voltage to decide.

2) Dynamic power, the power consumption of the circuit in active mode. Even if the output does not change, the input may also cause power dissipation due to transition.

Internal power, including power dissipation for internal circuit flushing and short circuit power dissipation. Low times,short-circuit for fast transition.

For slow transition times,short-circuit is relatively high.

The output capacitance of the switching Power,cell is flushed and discharged.

Set_power_derate: The percentage of power used to set a design,cell,library cell,hierarchical,leaf cell.

Report_power_derate

PTPX can put a design's power data in a power model and get the model by Extract_model-power.

You can speed up the progress of the Chip_level power analysis by using the way you instantiate it in your design. (Generate a. lib file)

The DESIGN,PTPX for gate_level generates a power model with a clock pin that can be used to analyze the power dissipation of a complex macro cell.

Power Analysis Input:

Logic library, which contains timing and power information, supports NLPM and CCS types of library.

Gate_level netlist, supports Verilog,vhdl,systemverilog format.

Design constraints, calculate primary input transition time and define clock.

activity,vcd/saif,default,user_defined.

NET Parasitic,spef file that contains the net RC parameter.

1) Set Power_enable_analysis is true.

2) read into the VERILOG,VHDL,DB,DDC format of the Netlist,logic library for the DB format.

3) Read the Spef file, including the WLD definition, as well as the SDF file, including the glitch.

4) Set_operating_conditions SET PVT.

5) for some fanout higher than net (clock reset), set Power_limit_extrapolation_range.

6) When timing data is not yet in the update, PTPX automatically timing analysis first, or it can be explicitly called by update_timing.

7) Check_power Check for potential power calculation issues, with Out_of_table_range and missing_table checked by default.

8) Set the mode of power analysis, Set_app_var Power_analysis_mode Average | Time_based.

9) Specify switching activity data, mainly set_switching_activity,set_case_analysis.

Read_vcd-time (Join time window)/-when (Boolean condition).

If a VCD and other waveforms are obtained from the RTL, a mapping file is required to match the waveform to the netlist.

Update power begins analysis of power analyses.

) Report power to the Power report.

Time_base's report has several more than the average report.

12) Finally save and extract the session through Save_session and Restore_session.

PTPX Power Analysis Flow