Quartus II warning and cause I encountered-continuous update

1. Warning (10227): Maid port declaration warning at press_modele.v (29): Data Type Declaration for "ir" Declares packed dimensions but the port Declaration declaration does not.

Explanation:

2. Warning: PLL "de2_ TV: inst1 | sdram_control_4port: U6 | sdram_pll: sdram_pll1 | altpll: altpll_component | PLL "output port CLK [0] feeds output pin" dram1_clk "via non-dedicated routing -- jitter performance depends on switching rate of other design elements. use PLL dedicated clock outputs to ensure jitter performance

Explanation: the PLL output is used in non-exclusive pll_out

Measure: it is best to use pll_out on the relevant clock signal when designing the circuit board. If it is not used, ignore this warning.

3. Warning: using design file CPU. V, which is not specified as a design file for the current project, but contains definitions for 25 design units and 25 entities in Project

Explanation: the module is not generated in this project, but directly copies the schematic diagram and source code of other projects.ProgramThe generated file is not added to this project using Quartus.

Measure: ignore it and avoid affecting usage.

4. Warning (10240): Maid (153): inferring latch (es) for variable "lut_data ", which holds its previous value in one or more paths through the always construct

Explanation: signals are integrated into latch. There is a competition between the latch en and the data input port.

Measure: extract the counter from it.

5. Warning: 12 hierarchies have connectivity warnings-see the connectivity checks report folder

Explanation: some ports are useless during instantiation, leaving the location of unused ports empty,

Measure: Ignore

6. Warning: synthesized away the following node (s)

Explanation: The following nodes are comprehensively optimized

Measure: Ignore

7. Warning: Found XX output pins without output Pin Load capacitance assignment
Explanation: The load capacitor is not specified for the output discipline

Measure: This function is used to estimate TCO and power consumption. You can ignore this function, or specify a load capacitor for the corresponding output pin in assignment editor to eliminate warnings.

8. Warning: The following nodes have both Tri-State and non-tri-state drivers

Explanation: Signals driven by three-state logic are driven by non-three-state logic.

Measure: locate the alarm in the sub-information and use the triplicate logic driver instead.

9. Warning: latch de2_ TV: inst1 | i2c_v_config: i2c_av_config | lut_data [8] has unsafe behavior

Warning: ports d and ENA on the latch are fed by the same signal de2_ TV: inst1 | i2c_v_config: i2c_av_config | lut_index [4]

Explanation: latch is generated.

Measure: Replace the combination circuit with time series, or use the complete if/else and case statements.

10. Warning: Tri or opndrc n buffers permanently Enabled

Explanation: three-state control is required for output.

11. Warning: Output pins are stuck at VCC or Gnd

Explanation: These output pins are directly grounded.

Measure: If this meets your design requirements, this warning can be ignored.

12. Warning (15400): WYSIWYG primitive "de2_ TV: inst1 | platform: U6 | platform: write_1_o2 | dcfifo: dcfifo_component | platform: auto_generated | platform: kerbero_ram | role: altsyncram5 | ram_block6a15 "has a port clk1 that is stuck at Gnd

Explanation: here the read/write mode of SDRAM is 1-in 2-out, and the input signal of ipvo2 is sent to Gnd.

Measure: Ignore it.

In addition, if a ram-related WYSIWYG primitive error or warning occurs, it is caused by the failure of the ram input signal.

13. Warning: Design contains 2 Input Pin (s) that do not drive Logic

Explanation: two inputs do not drive any logic. That is to say, only two input pins are defined, but these two input signals are not used in the logic.

Measure: remove the definitions of the two input pins.

14. Warning: at least one of the filters had some problems and cocould not be matched.

Explanation:

Measures:

15. Warning: node: XXX was determined to be a clock but was found without an associated clock assignment.

Explanations and measures:

(1) Is this expected clock signal? Or is it possible for the synthesizer to combine common signals into clock signals by mistake? Are thereCodeUsed the rising or falling edge of the signal?
(2) If it is the expected clock signal, is it possible to adjust the pin position to constrain it to the dedicated clock pin? If not, the online latency of the clock will be relatively large. However, the entire layout and wiring can continue.

16. Warning: PLL "de2_ TV: inst1 | sdram_control_4port: U6 | sdram_pll: sdram_pll1 | altpll: altpll_component | PLL "is in normal or source synchronous mode with output clock" compensate_clock "set to CLK [0] that is not fully compensated because it feeds an output pin -- only plls in Zero Delay buffer mode can fully compensate output pins

Explanation:

Measures:

17. Warning: PLL "de2_ TV: inst1 | sdram_control_4port: U6 | sdram_pll: sdram_pll1 | altpll: altpll_component | PLL "output port CLK [0] feeds output pin" dram1_clk "via non-dedicated routing -- jitter performance depends on switching rate of other design elements. use PLL dedicated clock outputs to ensure jitter performance

Explanation: FPGA-specific PLL output pins are not used.

Measure: Same as 2

18. Warning: ignored locations or region assignments to the following nodes

Warning: node "field" is assigned to location or region, but does not exist in Design

Explanation: some pins are allocated, but they are not used in the design.

Measure: Ignore it.

19: Warning: following 1 pins have no output enable or a Gnd or VCC output enable-later changes to this

Connectivity mayChange fitting results

Explanation: There is no output enabling for one pin below, or it is just a Gnd, VCC enabling

Measure: Configure an enable for it.

20. Warning: following 4 pins have nothing, Gnd, or VCC driving dataIn port -- changes to this connectivity may

Change fitting results

Explanation: Same as 11

Measure: Same as 11

21. Warning: the reserve all unused pins setting has not been specified, and will default to 'as output driving

Ground '.

Explanation: all unused pins are directly connected to Gnd

Measure: ignore it or modify it in assignments.