Quartus implementation of Nios II test (unfinished)

Prerequisites: Before the plan Ahead, XPS, SDK to build Xilinx Zynq 7000 (zerdboard) on-line test of PS and PL, try to define the platform, bus and DMA, see the previous blog.

Take the strike, last time. Altera's Nios II on the 3C120 chip RAM running light test.

Platform: Quartus + NIOS II EDK 10,3c120+epcs16 (+) +CFI Flash + Sdram (Sram), which is standard.

1, build Quartus hardware platform:

The Pll+le module (FPGA ontology logic module) +nios core (Nios) is equivalent to the SOPC + FPGA design.

1, 1 Open quartus:

To set the chip, configure the PIN for the EPCS--FALSH:

(Skip using EPCs, here is the Cyclone 3 environment, to set the EPCs falsh four pins as regular IO, configured after the FPGA as regular flash to store Nios program).

1, 2 configuration generated SOF, POF files:

The same is in assigned, device, under:

1, 3 new graphic design file Bolck digama/schematic file:

Double-click the blank space to add the PLL module:

1, 4 self-test a LED lit file, and then compile, navigation bar right-click File generated creat Synbom file, added to the design file:

Library IEEE;
Use Ieee.std_logic_1164.all;
Use Ieee.std_logic_arith.all;
Use Ieee.std_logic_signed.all;

Entity my_f_led is
Port
(
Clk:in std_logic;
Rst:in std_logic;


F_usr_led:out std_logic_vector (1 Downto 0)
);
End;

Architecture arch_my_f_led of my_f_led is

Signal clk_5m:std_logic;

Begin

Proc1_car_calcu:process (Clk,rst)
Variable proc1_state:std_logic_vector (7 Downto 0);
Variable Proc1_i:integer range 0 to 15;
Variable proc1_cnt:std_logic_vector (0 downto);

Begin

If rst = ' 0 ' Then
Proc1_state: = (others=> ' 0 ');
Proc1_i: = 0;
PROC1_CNT: = (others=> ' 0 ');
elsif Rising_edge (CLK) Then

PROC1_CNT: = proc1_cnt + x "000001";

f_usr_led (0) <= proc1_cnt (22);
f_usr_led (1) <= proc1_cnt (23);

End If;
End process;

End arch_my_f_led;

1. Choose tool Sopc Builder on the 5 menu, generate a sopc, name yourself, add nios free core, add Jtag UART, PIO, EPCs Flash, SDRAM, System ID, etc.

Added on the chart, the intended start is:

The Nios nuclear program exists on EPCs Flash (or CFI falsh) (selected by the reset vector) and runs on Onchip RAM or SDRAM (SRAM, drop-down selection) (Exception vector selection).

1, 6 next menu, system-"Auto--assgin Interrupt and base address, then next, generate Sopc file and module, wait a long time to complete save exit.

1, 7 join the Nios kernel under project. With the pin. Pll+pl+nios:

1, 8 to open the QSF file before compiling, the EPCs regular IO configuration:

Note the pre-and post-order (set regular IO before pin assignment), the IO voltage in the pin planer is set to 3.3V, because the EPCs configuration voltage is 3.3V.

Next save the file, compile generated sof and POF, occupy resources is more than 2000 le.

2. Next Open Nios IDE, build Nios Software

2, 1 new application C + + project, choose Helloword Template, change the program into LED.

2, 2 Select the Hello Word 0 project in the navigation bar, right-click Build project (Note that debugging is debug, the release version is finished).

Debug after compilation is quartus download sof file, that is, JTAG interface, and then select the project run as Nios hardware;

Operation is Flash program,cable is also connected to the JTAG. Here are the two corresponding graphs.

2, 3 library files and compile to reduce the volume, here the program. Text and Rodata select CFI Flash in the CFI falsh operation mode;

I want to choose EPCs falsh, compile always prompt epcs full can't put down, cause this place stuck dead can't continue.

In debug mode (run in RAM, power off disappears), either SDRAM or RAM is selected.

Summary: Nios I currently only implement in the Run as Hardware debug mode (library files are selected RAM);

Program segment placed on EPCs flsh compilation old error, unable to proceed to the next step;

The program segment is placed on RAM to Progarm to EPCs Flash, but the ple part Ok,nios run up after the power-down.

Come here first, after all, not the standard operating environment.

Quartus implementation of Nios II test (unfinished)