Quartusii Error (Error (10170): Verilog HDL syntax error at SDRAM_CONTROL.V (in) near text "' H"; Expect

Error (10170): Verilog HDL syntax error at SDRAM_CONTROL.V (in) near text "' H"; Expecting ";"

For the parameters defined internally in the. v file, parameter the reference with a ' number;

For example:

The parameter defined are as follows

Parameter asize=23; Total address width;
Parameter dsize=16; The data width is 16 bits;
Parameter sc_cl=3; After the instruction delay is 3CLK;
Parameter sc_rcd=3; The delay in reading data from SDRAM;

At the time of reference,

Assign Mdatain=wr_mask? Mdatain1:dsize ' hzzzz; When used for expansion, select the correct data to write to SDRAM;
Assign Dq=oe?  Mdatain:dsize ' hzzzz; In order to avoid data conflict, control bidirectional data pin;

The error will be as follows:

Change to band ' hereafter as follows: