"Brother Sopc Learning Notes" Several settings to note in software after switching the main memory of Nios II CPU

Several settings to note in the software after switching the main memory of the Nios II CPU

Sometimes, we may face a situation where:

1. We create a SOPC system and set the reset address and the exception address of Nios II in the Qsys to point to SRAM;

2. We have created the correct Nios II software engineering and are able to operate properly

3. Due to a demand (such as SRAM memory is not enough, need to replace the memory of the SDRAM), we in the face in the Qsys nios II CPU Reset address and the exception address modified to SDRAM

4. We need to continue to use the Nios II software project created previously.

Here, if we change directly using the original software engineering, then compile will error, so we need to re-map the allocation of individual data segments in the BSP editor, and then re-generate BSP, otherwise it will cause the firmware cannot be burned or burned after the program cannot run.

For example, in the Nios II tutorial code provided by the core Route FPGA Development Kit, our 5th and 6th experiments are running the same software engineering (Serial Drive design experiment) in SRAM and SDRAM respectively. Our 6th Experimental Qsys system adds SDRAM directly to the 5th experiment, and switches the Nios II CPU's reset address and the exception address from SRAM to SDRAM. At this time, if we directly open the previous Nios II software engineering, compile will error. (The default user here already knows and changes the BSP project path in the settings.bsp file, if you don't know how to change it, see my blog post:)

We check the BSP setting at this time: "Check uart_hal_bsp project", "right click Select Nios II", "Select BSP Editor in the submenu" as shown in:

In the popup screen, switch to the "Linker Script" tab, you can see that each data segment is still pointing to the SRAM, it is obviously wrong, so we click on the "Restore defaults" button. Click OK in the dialog box that pops up.

The location of the data segments is then updated to the SDRAM. As shown in the following:

This time we then click on the Generate button in the lower right corner, you can regenerate the BSP, and then compile the project, the download will be able to pass, and correctly run.

If you have more questions, welcome to join the core Route FPGA Technology Support Group Exchange Learning: A group of 472607506 (full) two group 615381411

Brother Mei

Core Route Electronic Studio

"Brother Sopc Learning Notes" Several settings to note in software after switching the main memory of Nios II CPU