"Design and development" typical asynchronous circuit design-Pulse synchronization (2)

First, preface

A simple pulse synchronizer has been described in the previous article, which allows for synchronization in simple scenarios, as well as a number of application limitations or drawbacks, such as:

(1) It is sensitive to the DST_CLK relation of SRC_CLK domain, and may not adapt when the SRC_CLK and DST_CLK clock frequency differ greatly;

(2) because there is no complete handshake mechanism, when the interval between multiple src_pulse is short, there may be a pulse synchronization loss situation.

(3) The SRC_CLK clock domain will be lost when there is no clock or reset in the DST_CLK clock domain.

This article will improve the Synchronizer to meet more asynchronous pulse synchronization scenarios.

Second, the principle

Review the basic design principles of the Synchronizer in the previous article:

(1) The source clock domain pulse is converted to the source clock domain level signal;

(2) The asynchronous processing of single bit level signal for beating;

(3) Pulse reduction in the destination clock domain.

From the above design principle, we can find that the control transmission of the Synchronizer is unidirectional, that is, only from the source clock domain to the destination clock domain, the destination clock domain does not have the state feedback. Suppose there are applications like:

(1) The first pulse and the second pulse interval in the source clock domain are too short, the first pulse is not synchronized, and the second pulse clears the state, resulting in the loss of the final pulse synchronization.

　　

To solve the above synchronization problem, it is necessary to introduce the asynchronous handshake mechanism to ensure that each pulse is synchronized successfully and then the next pulse is synchronized after the synchronization is successful. The handshake principle is as follows:

Sync_req: Source clock domain synchronous request signal, high level indicates that the current pulse needs to be synchronized;

Sync_ack: The destination clock domain response signal, high level indicates that the synchronization request is currently received;

　　

The complete synchronization process is divided into the following 4 steps:

(1) Synchronous request generation; When the Synchronizer is idle (that is, the last synchronization is completed), the synchronization request signal Sync_req when the source synchronization pulse arrives;

(2) The synchronous request signal sync_req synchronized to the destination clock domain, the target clock domain produces the pulse signal and generates the response signal sync_ack;

(3) The synchronous response signal Sync_ack synchronization to the source clock domain, the source clock domain detects the synchronous response signal Sync_ack, clears the synchronous request signal;

(4) The target clock domain detects the Sync_req revocation, clears the sync_ack answer; After the source clock domain is cleared to sync_ack, it is considered that once the synchronization is complete, the next pulse can be synchronized.

Third, the Code

//--====================================================================================--//This is the provided in SOURCE FORM for the free EVALUATION, for the educational use OR for//Peaceful. Do not use IT in A commercial PRODUCT. IF you PLAN on USING the This//CODE in A commercial PRODUCT, click Contact [e-mail protected] to properly LICENSE//Its use in YOUR PRODUCT.// //project:verilog Common Module//File NAME:HANDSHAKE_PULSE_SYNC.V//Creator (s): [email protected]//date:2015/12/01//description:a handshake Pulse Sync////Modification://(1) Initial design 2015-12-01//////--====================================================================================--module Handshake_pulse_sync (SRC_CLK,//Source ClockSrc_rst_n,//source Clock Reset (0:reset)Src_pulse,//source Clock pulse inSrc_sync_fail,//Source clock sync state:1 clock pulse if sync fail.DST_CLK,//Destination ClockDst_rst_n,//Destination Clock Reset (0:reset)Dst_pulse//Destination Pulse out    ); //PARA DECLARATION//INPUT DECLARATIONinputSRC_CLK;//Source ClockinputSrc_rst_n;//source Clock Reset (0:reset)inputSrc_pulse;//source Clock pulse ininputDST_CLK;//Destination ClockinputDst_rst_n;//Destination Clock Reset (0:reset)//OUTPUT DECLARATIONOutputSrc_sync_fail;//Source clock sync state:1 clock pulse if sync fail.OutputDst_pulse;//Destination Pulse out//INTER DECLARATIONWire dst_pulse, wire src_sync_idle; reg Src_sync_fail; reg                 Src_sync_req; reg Src_sync_ack; reg Ack_state_dly1; reg Ack_state_dly2; reg Req_state_dly1; reg Req_state_dly2; Reg dst_req_s Tate; reg Dst_sync_ack;//--========================module SOURCE code==========================--//--=========================================--//DST Clock://1. Generate Src_sync_fail;//2. Generate Sync req//3. Sync Dst_sync_ack//--=========================================--Assign Src_sync_idle = ~ (Src_sync_req |src_sync_ack);//Report a error if src_pulse when sync busy;Always @ (Posedge SRC_CLKorNegedge src_rst_n)begin    if(Src_rst_n = =1'B0)Src_sync_fail <=1'B0;    Else if(Src_pulse & (~src_sync_idle)) Src_sync_fail<=1'B1;    ElseSrc_sync_fail<=1'B0;End//Set Sync req if src_pulse when sync idle;Always @ (Posedge SRC_CLKorNegedge src_rst_n)begin    if(Src_rst_n = =1'B0)Src_sync_req <=1'B0;    Else if(Src_pulse &src_sync_idle) Src_sync_req<=1'B1;    Else if(src_sync_ack) src_sync_req<=1'B0;EndAlways @ (Posedge src_clkorNegedge src_rst_n)begin    if(Src_rst_n = =1'B0)        beginack_state_dly1<=1'B0;Ack_state_dly2 <=1'B0;Src_sync_ack <=1'B0;         End        Else        beginack_state_dly1<=Dst_sync_ack; Ack_state_dly2<=ack_state_dly1; Src_sync_ack<=Ack_state_dly2; End        End//--=========================================--//DST Clock://1. sync src sync req//2. Generate DST Pulse//3. Generate Sync Ack//--=========================================--Always @ (Posedge DST_CLKorNegedge dst_rst_n)begin    if(Dst_rst_n = =1'B0)        beginreq_state_dly1<=1'B0;Req_state_dly2 <=1'B0;Dst_req_state <=1'B0;        End    Else        beginreq_state_dly1<=Src_sync_req; Req_state_dly2<=req_state_dly1; Dst_req_state<=Req_state_dly2; EndEnd//Rising Edge of dst_state generate a dst_pulse;Assign Dst_pulse = (~dst_req_state) &Req_state_dly2;//set Sync ack when Src_req = 1, clear it when src_req = 0;Always @ (Posedge DST_CLKorNegedge dst_rst_n)begin    if(Dst_rst_n = =1'B0)Dst_sync_ack <=1'B0;    Else if(req_state_dly2) Dst_sync_ack<=1'B1;    ElseDst_sync_ack<=1'B0;EndEndmodule

Four, simulation

(1) When the target clock domain dst_rst_n Reset, the pulse is not lost;

　　

(2) normal synchronization situation;

　　

(3) High frequency of source pulses;

　　

　　

"Design and development" typical asynchronous circuit design-Pulse synchronization (2)