"FPGA full-step---practical walkthrough" to fix Impedance matching

The author in recent days in the video capture board card, video display end intends to use USB2.0 interface + host computer display, wherein the USB needs to do impedance matching. Typically, USB impedance values need to be 90ω±10%. The following is about the impedance matching knowledge, where said wrong, but also hope that you criticize correct.

In high-speed circuits, such as USB, HDMI, DDR, LVDS design is often to pay attention to the problem of impedance matching, high-frequency signals in the transmission line to meet the resistance is called the characteristic impedance, including capacitance resistance, inductance, impedance. In order to ensure that the signal does not occur during transmission, the signal is kept intact and the transmission loss is reduced, and the impedance of the printed circuit board is matched. The purpose of impedance matching is mainly that all high-frequency microwave signals on the transmission line can reach the load point, and no signal will be reflected back to the source. Typically, the impedance value of the usb/ddr remains at 90ω±10%. Hdmi/lvds remained in 100ω±10%.

The key factors affecting the impedance are shown in 25.1, there are: line width (w), line spacing (s), line thickness (t), dielectric constant (dk/er), media thickness (H), then impedance and line width (w), line spacing (s), line thickness (T), dielectric constant (dk/er) is inversely proportional to the dielectric thickness (H).

Fig. 25.1 influence factors of impedance

Figure 25.2 Impedance related factors

Impedance matching method: 1. By experience value, 2. to PCB manufacturer; 3. Combined with SI9000, the theoretical calculation of the system is carried out. Then this section is mainly about the use of SI9000.

Figure 25.3 shows the different plate thickness of the parameters of the setting, this figure is not a standard, only as a guide, by the figure of 1.2mm thickness of the board and 1.6MM Board is the thickness of the insulating layer is not the same, the other parameters remain consistent. If you use Altium friends, you should remember that when you set up the layer, there is a core and prepreg,25.4, the difference between core and Prepreg is that, although all are insulating material, but the core can have both sides have copper wire traces, prepreg for pure insulating material, Do not take any copper wire.

Fig. 25.3 parameters of different plate thickness of four-ply plate

Figure 25.4 The parameters of the four-layer board in Altium

Figure 25.5 is an introduction to the SI9000 interface.

Figure 25.5 SI9000 Interface

Usually, the power layer and stratum are used as the signal layer current return path and impedance reference layer, and the stratum is generally used as the reference layer or current return path. If the power layer must be used as a reference or as a path for signal backflow, be careful not to allow high-speed signal-line coupling noise to the power plane.

Then the following is a combination based on USB video capture board to illustrate the calculation of impedance and line width and spacing problems.

Figure 25.6 USB2.0 Hardware Setup

As shown in 25.6 is the USB2.0 hardware circuit diagram, wherein the dplus and Dminus cabling directly determines the final transmission speed. For USB hardware cabling and related design, readers can refer to Cypress related file contents. As shown in 25.7.

Figure 25.7 Related references

On the PCB panel, the USB d+ (dplus) d (Dminus) is two conductors, generally parallel, affecting the d+ (Dplus) and D (dminus) differential impedance factors as mentioned earlier.

Using the 2D model of the microwave transmission belt in the electromagnetic wave principle, the single-root impedance is calculated as follows:

The differential impedance model is shown in 25.8.

Figure 25.8 Differential Impedance model

The differential impedance is calculated as follows:

After understanding the above principles, we can directly use SI9000 this software to calculate, do not have to remember those tedious formula, but from the above formula, you can also see that the impact of the impedance and the first mentioned factors are consistent.

I designed the arrangement of the four-layer panel: Top layer (signal layer)---power plane (inner plane)---GND layer---bottom layer (signal layer), so I calculate the impedance, A reference plane can be selected for both power and stratum, so the top layer (signal layer)---power plane (inner plane) can be computed, and the GND layer---bottom layer (signal Layer).

Open the SI9000 software (software can be downloaded online), first calculate the single-ended impedance, the actual model, the manufacturer will often apply a layer of green oil on the top layer, so the actual model as shown in 25.9:

Figure 25.9 Single-ended impedance

I designed the single-ended impedance correlation parameter 25.10 shows that the calculated result is a single-ended impedance value of 69.73, in general, the single-ended impedance to retain a certain amount of margin. The author tolerance A not set, this specific should be and PCB manufacturer communication, so this parameter can meet our design requirements.

Figure 25.10 Single-ended impedance parameter

After the single-ended impedance is fixed, the next step is to calculate the differential impedance, which should be kept within the 90ω±10% range as far as possible. SI9000 Select interface 25.11 as shown.

Figure 25.11 Differential Impedance

After design, you need to set the relevant parameters, as shown in 25.12:

Figure 25.12 Differential Impedance correlation parameters

The spacing is 6mil, the thickness of the line width is 15mil,core layer is 12.6mil, the calculated result is 89.72ω, satisfies within the 90ω±10% range.

Once the above parameters have been calculated, the wiring must be started, then the differential pair should be set in the schematic diagram. As shown in 25.13. It is defined by choosing place---directives---differential pair in the menu bar, and also note that the names need to be defined as *_n and *_p formats, where the N and p sections are case-sensitive.

Figure 25.13 Definition of a differential pair

After defining the parameters, you need to set the rules for the differential pair, as shown in 25.14, click the Rule Wizard.

Figure 25.14 Rule Settings

According to the above calculation, the line width is 15mil best, so set the line width to 15mil.

Figure 25.15 Line width settings

Considering PCB cabling, the length of the d+ (Dplus) and D-(Dminus) lines is less than 70mm to 20~30mm, and d+ (Dplus) and D (Dminus) lines should be as low as 2mm to prevent signal delay. So, as shown in Figure 25.16, the conversion to a mil value is 80mil.

Figure 25.16 Allowable length Difference range

Figure 25.17 is the spacing setting, preferably 6mil pitch.

Figure 25.17 Spacing settings

Next, the wiring can be routed using the differential pair routing function.

"FPGA full-step---practical walkthrough" to fix Impedance matching