"I know bios"->pci (pic) __ios

"I know bios"->pci (pic)

Lightseed

2009-5-13 1, PCI overview

Note: The whole article is discussed in the PIC (8259) in the process of the process. When the PCI devices are plugged into the motherboard (which is included in the South Bridge), it wants to communicate with other devices, or let the CPU do it like this, or the CPU let it do so ... So how do they communicate with each other? This is the strong effect of PCI on the middle. PCI, there is a very large special point, it can be shared. I'm going to start with this special, and I'll do a cobblestone cushion. 2, PCI in the interrupted HW

When it comes to PCI, I want to say it first. The device that we use to scan the program is logically device. For example, the device in Bus#0dev#31fun0 is a logical device. And even when we say a PCI card, a PCI card, they are all physical device. A physical device may have multiple logical device. This is actually the meaning of function. The logical device is actually a function. Here to find out. Diagram 2.1 is an abstract diagram that is disconnected from the PCI setup.

The PCI facility connects to 8259 with the INTA~INTD pin to transmit the signal. It should be stated that the PCI devices for single function can only use INTA.

PCI (pic) __ios ">

Graph 2.1 PCI Setup in the abstract diagram

As shown in Figure 2.1, the Intx connection that is drawn up is connected to the 8259 Pirqa~d by the routed route. 3, Intx of the line

The people in the heart will find that the links in image 2.1 are orbiting. So why does HW have to do this? This involves the concept of "loading balance". The following is a post from the programming club, original author Liaoo

"The Interrupt pin was decided when it was out of the factory and cannot be changed. Ex. Use the SE or ru check PCI REG3DH = 01/02/03/04 for int#a/b/c/d. And interrupt line is the BIOS when it knows "routing" to fill in. For example, the BIOS knows

Int#a will eventually receive 8259 IRQ 11 in PIC mode, and PCI reg3ch be filled in as "0Bh" at the PCI scan stage. As you say how to connect, PCI spec has mentioned, for "Loading balance", board designer can decide. Ex. 2 PCI devices, all are int#a interrupt (so their PCI REG3DH = 01h). The two were on the same board. If, board designer decides to: (The following is the method of the Assumption)

PCI slot1: Int#a received I-router int#b,int#b received I-router int#c,int#c to I-router received int#d,int#d I-router of PCI int#a received: I Nt#a received I-router Int#a,int#b received I-router Int#b,int#c received I-router Int#c,int#d received I-router

When 2 PCI devices receives slot1 and 2, it happens: although it is interrupt through the int#a, the last is from "different source" (Device 1 from int#b, Device 2 from int#a. ..)” 4, assign IRQ to PCI equipment.

As mentioned above, after a good detour, the routing Intx are connected to the pirqa~d. The BIOS kernel the calculated PCI IRQ No. Assigned to Pirqa~d. Say Pirqa~d irq5,irq9,irq5,irq9. Then the devices that are eventually connected to the Pirqa are assigned to IRQ5. The allocation of this PCI IRQ is complete. 5, about the description of the PCI IRQ

Some people are sure to ask why the top Pirqa and PIRQC IRQ No. are 5. How does this communicate? Oh, your worry is normal, but the engineers have solved the problem. The first part of the article mentions that a PCI IRQ can be shared. Here they are sent to use the scene. 6, about PCI IRQ Routing Table 6.1 PCI IRQ Routing table Complex

A few of the above we talk about the hot fire, only the intx of the PCI facility is connected to the pirqy of South Bridge so that the IRQ No can be correctly allocated to the corresponding PCI. But here's the downside: the OS or other software doesn't know how the intx of a certain set of hardware and the pirqy of the South Bridge are responding. The OS or other software cannot correctly allocate IRQ No in a worthwhile situation. to the facility. Then this PCI IRQ Routing table stands up to the role of describing the hard information. It is the most important in the entire IRQ allocation process. So let's analyze its structure. 6.2 The structure of a PCI IRQ Routing Table

Byte Offset	Size in Bytes	Name
0	4	Signature
4	2	Version
6	2	Table Size
8	1	PCI Interrupt Router ' s bus
9	1	PCI Interrupt Router ' s devfunc
	2	PCI Exclusive IRQs
	4	Compatible PCI Interrupt Router
	4	Miniport Data
	One	Reserved ( Zero)