"On-Chip FPGA Advanced Learning Tour" ddr2+ Gigabit Ethernet circuit design based on Altera FPGA

Source: Internet
Author: User

DDR2 Circuit Design

High-speed large-capacity cache is an essential hardware in high-speed big data applications. At present, the use of a wide range of high-speed large-capacity memory in FPGA system has a classical low-speed single data rate of SDRAM memory, and high-speed dual-rate DDR, DDR2, DDR3 type SDRAM memory, The DDR series of memory all require the FPGA chip has the corresponding hardware circuit structure support. For the Altera Cyclone IV series FPGAs, they support up to DDR2 memory (DDR3 memory is not supported and DDR3 memory is supported in Cyclone V series FPGAs). Core Route AC6102 Development Board as a high-speed application Development Board, in order to ensure the storage bandwidth and capacity of the system, the circuit design a set of 32-bit DDR2 memory, interface clock rate of up to 200MHz, the equivalent data rate of 400MHZ, the overall system bandwidth of 32bit*400m = 12.8gb/s.

DDR2 and FPGA connection mode

Each piece of DDR2 memory capacity is 1Gb, two DDR2 chip combination, get total capacity of 2Gb. The single DDR2 memory is 16bit, the two pieces of memory share the control line and the address line, the data line is parallel, namely the 32-bit 2GB storage module.

As shown in the following:

    • Two pieces of DDR2 cs, WE, CAS, RAS, CLK, CKE, ODT, ADDR, bankaddr are connected together
    • Ddr2_1 16-bit data cable dq[15:0] as low 16-bit data cable for 32-bit DDR2 storage circuit connected to FPGA, ddr2_dq[15:0]
    • Ddr2_2 16-bit data cable dq[15:0] High 16-bit data cable as 32-bit DDR2 storage circuit connected to FPGA, Ddr2_dq[31:16]
    • The Ddr2_1 2-bit DQS and DM are connected to the FPGA, respectively, as the dqs[1:0 of the 32-bit DDR2 storage circuit] and dm[1:0]
    • The Ddr2_2 2-bit DQS and DM are connected to the FPGA, respectively, as the dqs[3:2 of the 32-bit DDR2 storage circuit] and Dm[3:2]

DDR2 Power supply Design

The DDR2 circuit uses 1.8V power supply, in order to ensure that the DDR2 can have sufficient energy to run, using the board power chip TPS650243 DCDC output as DDR2 1.8V power supply,

In addition, the DDR2 reference power stability also directly determines the stability of the DDR2 work, DDR2 Reference supply voltage of the operating voltage of half, that is 0.9V. In a general low-cost design, the voltage can be obtained using two 1%-precision resistor-divider voltages. AC6102 in order to ensure that DDR2 work is absolutely reliable, the use of dedicated DDR series memory supply Chip lp2996m, the power supply can be accurate and stable DDRX chip operating voltage of half of the output as a DDR2 reference source (VREF), and can provide DDRX series of terminal voltage Supply (VTT), VTT is in the DDR2 need to shunt the terminal resistor, to provide power supply for the terminal resistor, only in the parallel use of more than 2 DDR2 chips to consider the need for parallel terminal resistors, this design uses only 2 DDR2 chip, Therefore, the VTT output of the chip is not needed in practice.

Pin assignment strategy when FPGA is connected to DDR2

The DDR2 is a high-speed, large-capacity memory with an interface clock rate of up to 200M and a DDR mode with a real interface data rate of 400M. At this high interface rate, the FPGA pin assignment is also quite fastidious, according to the Altera Cyclone IV series device Manual, when the IO port is configured in a single-ended mode, the speed level of C8 devices, up to two bank up to 167 MB of IO rate, The left and right two banks can only support up to 133.3M, so, for DDR2, the pins need to be distributed in bank3+4 or bank7+8. Of course, if you use C6 devices, BANK3, 4, 7, 8 (that is, up and down the bank) can reach 200M, while BANK1, 2, 5, 6 (that is, the left and right bank) only reach 166.7M.

The following conditions are required for pin assignment of the DDR2:

    • Hope for high speed, as far as possible to allocate in BANK3+BANK4 or BANK7+BANK8
    • Data bus according to 8-bit or 16-bit grouping, for 256 feet of this device, due to a limited number of pins per bank, it is recommended that the low 8-bit and high 8 bits are allocated in the same bank, while the corresponding DQS and DM should also be assigned to the corresponding bank of DQ data. For devices with 484 or more pins, each 16-bit data line and the corresponding DQS and DM are assigned to the same bank
    • The IO level of the DDR2 is 1.8V, so the FPGA is connected to the DDR2 bank and its IO supply voltage should be 1.8V
    • As mentioned above, the DDR2 IO level flavor 1.8V, so the FPGA corresponding to the bank's IO supply voltage page should be 1.8v,ac6102, DDR2 and FPGA BANK3 and BANK4 connection, so the FPGA chip corresponding IO The Bank power supply is set to 1.8V, as shown in:

Through this section, we understand the FPGA connection DDR2 chip circuit principle and considerations, we can according to their own needs, combined with the schematic diagram we provide, design their own hardware and software systems. If you have special needs, you can contact us for assistance.

Gigabit Ethernet Circuit Design

Ethernet interface as a kind of interconnected interface, the current application is very extensive. From home broadband, to server data exchange, to industrial control, Ethernet can be seen everywhere. FPGA system uses Ethernet, is mainly used for high-speed long-distance data transmission, such as LED large screen display, monitoring system and so on. Ethernet data link, also from the early telephone line transmission, to later dedicated twisted-pair, the development of optical fiber, high-frequency wireless power, and now relatively novel LiFi.

Ethernet and FPGA connectivity

The AC6102 Development Board provides a Gigabit Ethernet interface consisting of Gigabit Ethernet PHY and network transformer interfaces. When the Ethernet data needs to be sent, the FPGA sends the data to the PHY chip, and the PHY chip encodes the data and loads the data onto the network cable via the net transformer. Data is passed through the network to the receiving party. The data sent over the far end is transmitted to the network transformer via a network cable, the output of the transformer is connected to the PHY chip, the PHY chip decodes the signal, obtains the actual data, then transmits the data to the FPGA chip. The functional block diagram of FPGA for Gigabit Ethernet data transfer is as follows:

Mode configuration

The RTL8211 is an Ethernet physical layer transceiver that supports GMII, RGMII, and Mii interfaces and is capable of working in 100M base or 1000M base mode. The interface can be set to Gmii, RGMII, MII interface. A number of pins are provided for configuring the operating mode.

AC6102 default use of the Gmii interface, the way to implement this configuration is the corresponding configuration pin E_col (yes, this pin, the chip on the power-up will detect the state of the pin, and according to the status of the pin to determine the operating mode, normal operation is normal COL function) by 10K resistor to GND.

The Ethernet physical layer chip has a device address, which can be set via an external pin, in which the R20, R21, and R24 are connected to VCC or GND, which determines the device address of the chip is 001b. Of course, these states are also only on the chip power time is read, when the chip is working properly, these pins have resumed normal function.

With FPGA pin connection AC6102 on Ethernet all signals connected to the FPGA are assigned to the BANK8 of the FPGA for a more ideal timing constraint effect. The following is the connection between the RTL8201 chip and the FPGA.

"On-Chip FPGA Advanced Learning Tour" ddr2+ Gigabit Ethernet circuit design based on Altera FPGA

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