"Reprint" Jointwave 0 delay video transmission for fpga/asic into the military field

Semiconductor intellectual Property h.264/h.265 Silicon IP Core supplier Jointwave company released a series of video codec RTL IP Core, has been successfully applied to the Military industry field of command combat, UAV UAV control, aviation and aerospace cameras, video recording black box and other applications

These IP check technical characteristics are as follows: The first feature is that video encoders and video decoders work together to achieve a zero-delay video transmission system, and only 0 delay can be applied to the field of military command warfare and UAV & avionics control. The second feature is visual lossless, 1-channel HD screen 1080p@60fps uncompressed data is 3Gbps, the use of H. Intra only mode using 4:4:4 color space, 3Gbps compression to 50mbps~500mbps can be solid line visual lossless, Realize 1-way 4Gbps fiber can transmit 8~20 1080p@60fps lossless video simultaneously. The third feature uses the H. Intra only compression without the need for external memory i.e. DDR particles. The fourth feature is the ultra-high resolution, the highest performance of a single h-coded IP core FPGA (Altera Stratix 10) platform for 4kx4k@30fps. The fifth feature is multi-channel, each H-coded IP core FPGA (Altera Stratix V) platform enables the implementation of 12-way encoding performance support 480p@30fps per channel. Other features such as: Color space support 4:0:0/4:2:0/4:2:2/4:4:4 color depth support: 8bit/. 10bit/12bit/14bit, compression ratio span 1/10~1/1000, the highest bitrate support 0~500mbps, commercial applications have broadcast encoders, telemedicine, wireless display WDE, video sites and so on.

Thomas Wang, president of Jontwave Asia Pacific, said: Jointwave H. IP Core and the second half of 2014 will be delivered to customers using the h.265 IP core First order, on the FPGA platform (Xlinx kintex-7&virtex-7 or Altera Cyclone V & Arria v) have the world's highest performance, the world's only set of 1080p@60fps 0 time-Delay codec based on the FPGA platform of a live demonstration system, the demo system is to provide customers with the closest to the final product real performance evaluation system.

Arria V 1080p@60fps 0 Time-lapse demo photo

This series of H. IP cores have been listed in the form of RTL source code for ASIC applications, or in the form of RTL source code and Web tables for programmable device FPGAs. In addition, Jointwave has formed several high-performance demonstration and reference design platforms. This reference design connects two FPGA boards or UDP interfaces to the PC via the UDP interface, which obtains video uncompressed data from the HD player. The FPGA is then encoded into the video, and finally the results are sent to the PC display and storage or sent to another FPGA board for decoding and display. These reference designs will not only significantly reduce the IP evaluation time of FPGA/SOC design engineers, but also facilitate the customer's prototype validation of the design.

"Reprint" Jointwave 0 delay video transmission for fpga/asic into the military field