"Turn" DDR3 detailed (Take micron MT41J128M8 1Gb DDR3 SDRAM as an example)

These two days are learning how the FPGA control DDR3 read and write, find a personal feel more meaningful article, you can have a preliminary understanding of the internal structure of DDR. Source: http://blog.chinaunix.net/uid-28458801-id-3459509.html, thank the Great God for the pay.

First, let's look at the general structure of the memory workflow, which compares the capacity to understand the role of these parameters in it. This section describes the use of DDR3 's simplified sequence diagram.

Inside the DDR3 is a storage array that "fills in" the data and you can think of it as a form. As with the table's retrieval principle, specify a row, and then specify a column, so that we can find exactly the cells we need, which is the basic principle of memory chip addressing. For memory, this cell can be called a storage unit, then the table (storage array) is the logical bank (Logical Bank, hereinafter referred to as the Bank).

DDR3 Internal Bank, which is a nxn array, B is the bank address number, C is the column address number, and r represents the line address number.

If the addressing command is B1, R2, C6, you can determine the address is the location of the red lattice in the graph.

At present, DDR3 memory chips are basically 8 bank design, that is, a total of 8 such "forms."

The process of addressing is to specify the bank address, specify the line address, and then the column address to the final addressing unit.

At present, the concept of the physical bank exists in the DDR3 system, which is a related term for the memory subsystem and not for the memory chip. Memory in order to ensure that the CPU is working properly, the data required by the CPU during one transmission cycle must be transmitted at one time. The amount of data that the CPU can accept in a transmission cycle is the bit width of the CPU bus, and the unit is bit. The North Bridge chip, which controls the data exchange between the memory and the CPU, also equates the data bit width of the memory bus with the bit width of the CPU bus, which is called the bit width of the physical bank (physical bank, some data is called rank). At present, this bit width is basically 64bit.

In the actual work, the bank address and the corresponding line address is issued at the same time, this command is called "Row activation" (row active). After this, the column address addressing command is sent with the specific operation command (read or write), and the two commands are also issued simultaneously, so the general will be "read/write command" to represent the column addressing. According to the relevant criteria, the interval between valid from line to read/write command is defined as TRCD, that is, RAS to CAS delay (RAS to CAS latency, RAS is the line address strobe pulse, CAS is the column address strobe pulse), we can understand the row strobe cycle. TRCD is an important timing parameter for DDR, in which the generalized trcd is in the number of clock cycles (Tck,clock time), such as trcd=3, which represents a delay period of two clock cycles, depending on the timing, depending on the clock frequency, ddr3-800,trcd= 3, which represents a delay of 30ns.

Trcd=3 is shown in the figure

Next, when the relevant column address is selected, the data transfer will be triggered, but the output from the storage unit to the I/O interface that really appears in the memory chip will also take some time (the data trigger itself has a delay, but also need to signal amplification), this time is very famous CL (CAS Latency, Column address pulse strobe incubation period). The CL value is the same as TRCD, expressed as the number of clock cycles. such as ddr3-800, the clock frequency is 100MHz, the clock period is 10ns, if cl=2 means 20ns incubation period. However, CL is only for read operations.

Because of the chip volume, the capacitance in the storage unit is very small, so the signal must be amplified to ensure its effective identification, the amplification/drive work by S-amp, a storage body corresponding to a s-amp channel. But it has to have a preparation time to ensure the signal transmission intensity (before the voltage comparison to the logic level of the judgment), so from the data I/O bus has a data output before the rising edge of the clock, the data has been transmitted to the s-amp, that is, the data has been triggered at this time, After a certain amount of drive time is eventually transmitted to the data I/O bus for output, this time we call the TAC (access time from CLK, after the clock triggered the access times).

Figure in Standard Cl=2,tac=1

Current memory reads and writes are basically continuous, because the amount of data exchanged with the CPU is based on the capacity of a cache line (that is, the storage unit of the cache in the CPU), typically 64 bytes. The existing rank bit width is 8 bytes (64bit), then a continuous transmission 8 times, which involves we also often encounter the concept of burst transmission. Burst (Burst) refers to the same row in the contiguous storage unit data transmission in a continuous manner, the number of consecutive transmission is the burst length (Burst lengths, referred to as BL).

In the case of a burst, as long as the starting column address and burst length are specified, the memory will automatically read/write to the corresponding number of storage units in the following order without requiring the controller to provide the column address continuously. Thus, in addition to the first data transmission requires a number of cycles (mainly the previous delay, typically TRCD+CL), then each data only need one cycle to obtain.

Burst continuous read mode: As long as the initial column address and burst length are specified, subsequent addressing and data read automatically, and as long as the control of two burst read command interval (same as BL) can be continuous burst transmission.

When it comes to burst length. If bl=4, then that means the 4x64bit data is transmitted at one time. But what if the second data is not needed? Are they still transmitting? In order to block unwanted data, people have adopted a data mask (DQM) technology. With DQM, memory can control which output or input data the I/O port cancels. It should be emphasized that, when reading, the masked data will still be removed from the storage, but masked at the "Mask Logical Unit". DQM is controlled by the North Bridge, in order to accurately shield each byte in a p-bank bit width, each DIMM has 8 DQM signal lines, each of which is directed at one byte. Thus, for a 4bit bit width chip, two chips share a DQM signal line, for 8bit bit width chip, a chip occupies a DQM signal, and for 16bit bit width chip, it requires two DQM pin.

After the data has been read, the memory chip will pre-charge the operation to close the current work line in order to vacate the readout amplifier for addressing and transmitting data to other rows within the same bank. Take the example of the bank diagram above. The storage units currently addressed are B1, R2, C6. If the next addressing command is B1, R2, C4, then pre-charging is not necessary because the readout amplifier is serving this line. But if the address command is B1, R4, C4, because it is a different row of the same bank, then the R2 must be closed before the R4 can be addressed. The interval between closing an existing work line and opening a new work line is the TRP (Row precharge command Period, row pre-charge active period), which is the number of clock cycles.

The same is true for reading and writing between different banks, first write back the original data, and then activate the new Bank/row.

Data selection pulses (DQS)

DQS is an important feature of DDR, its function is mainly used in a clock cycle to accurately distinguish each transmission cycle, and easy for the receiver to receive data accurately. Each chip has a DQS signal line, which is bidirectional and is used to transmit a DQS signal from the North Bridge when it is written, and is sent by the chip generation Dqs to the bridge when it is read. It is perfectly possible to say that it is a synchronous signal of data.

At read time, DQS is simultaneously generated with the data signal (also at the intersection of CK and ck#). In DDR memory, CL is the interval from the CAs to the Dqs generation, and when DQS is generated, the in-chip prefetching is complete, and the actual data egress may occur earlier than DQS due to prefetching (the data is earlier than DQS). Because it is a parallel transmission, DDR memory has certain requirements for the TAC, the allowable range for Ddr266,tac is ±0.75ns, and for DDR333, it is ±0.7ns, the timing diagram for them is described earlier, where CL contains a period of time for the import of DQS.

When DQS transfers data synchronously while it is being read, will it be received at the top and bottom edge of DQS? No, it is very risky to differentiate data cycles in the upper and lower edges of DQS. Because the chip has pre-fetching operation, so the output synchronization is difficult to control, can only be limited to a certain time range, the data in the various I/O ports may be fast and slow, and DQS have a certain interval, which is why there is a TAC rules for the reason. On the receiving side, everything must be guaranteed to be received synchronously, and there should be no deviations such as TAC. In this way, when writing, the chip no longer generates DQS itself, and by the sender of the DQS as a benchmark, and corresponding delay for a certain period of time, in the middle of DQS for the data period of the selection of the split point (the split point is the upper and lower edge when reading), from here to separate the two transmission cycle. The advantage of this is that because each data signal has a logic level hold cycle, the data receive trigger is undoubtedly the highest accuracy, even if it is not synchronized at the time of the DQS and is in the hold cycle when it is up and down.

At write time, the data period is divided by the middle of the high/low period of DQS, not the up/down edge, but the receiving trigger of the data is still the top/bottom edge of DQS

3. Calculation of the capacity

For X8data single DDR3 frame composition, row address line Multiplexing 14, column address line multiplexing 10, bank number is 8, IO Buffer through 8 groups of digital lines (DQ0-DQ7) to complete external communication, Therefore, the capacity of a single DDR3 chip is 2 14 times 2 of the 10 squares by 8 times 8, the result is 1Gbit, because 1B contains 8BIT,1GB/8=128MB.

If we want to make a 1GB memory chip will need 8 such DDR3 memory chips, each chip with 8 digits (DQ0-DQ7) is the total width of 64bit, so that just a rank.

Pseudocarp also use 128MB DDR3 chip to do 2GB memory, the result will be different. We had better choose 4 digit Line (DQ0-DQ3), the number is 16, this also used a rank.

In the K2 project we want to do the capacity of 8GB memory, then the number with 64 128M of DDR3, so the bit width up to 64x4=256bit, to make 4 rank.

1. Structural block Diagram:

2. Pin function Description

3. State diagram:

Power on: Power-on

Reset Procedure: Reset Process

Initialization: Initialization

ZQCL: After power-on initialization, calibrate the ZQ resistor with the completion. The ZQCL will trigger the internal DRAM calibration engine,

Once the calibration is complete, the calibrated value is passed to the IO pin of the DRAM and is reflected in the output drive and the ODT resistance.

ZQCS: Periodic calibration, which can follow changes in voltage and temperature. Calibration requires a shorter window of time,

Once calibrated, the minimum 0.5% Ron and RTT resistors can be corrected effectively.

Al:additive latency. Is a valid time to keep commands or data on the bus.

In the DDR3 allows direct manipulation of read and write operations, AL is the time the data on the bus appears to enter the inside of the device.

The time operation supported by the DDR3 standard.

Write leveling: In order to achieve better signal integrity, the DDR3 enclosure takes a fly_by topological structure,

To handle commands, addresses, control signals, and clocks. The topological structure of fly_by can effectively reduce the number of stubs and their length,

But it causes the clock and strobe signal to flight time skew on each chip, which makes the controller (FPGA or CPU)

It is difficult to keep tdqss, Tdss and tdsh these timings. This way, DDR3 supports the Write leveling feature,

To allow the controller to compensate for skew (flight time skew). The memory controller is able to tune the relationship between DQS and CK using this feature and the data that is fed back from DDR3.

In this adjustment, the memory controller can adjust the time delay of the DQS signal to align with the rising edge of the clock signal.

The controller continuously delays DQS until it discovers jumps from 0 to 1, and then the DQS delay is established in such a way that the TDQSS can be guaranteed.

Mrs:mode Register set, mode register setting. For the flexibility of application, different functions, features and modes are in the four mode register on the DDR3 chip,

Implemented by programming. The mode register Mr does not have a default value, so the mode register Mr must be fully initialized after power-up or reset.

This will enable the DDR to work properly. In normal operating mode, Mr can also be re-written. The set command period for the mode register,

TMRD two times the minimum time of operation, its specific timing diagram, as shown in. The mode registers are divided into MR0, MR1, MR2 and MR4.

MR0 is used to store data for different operating modes of DDR3: Burst length, read burst type, cas length, test mode, DLL reset, etc.

The MR1 is used to store whether to enable DLL, output drive length, rtt_nom, extra length, write level enable, etc. MR2 is used to store the features of control updates,

RTT_WR impedance, and CAs write length. MR3 is used to control MPR.

Mpr:multi-purpose Register. Multi-purpose registers. The function of MPR is to read out a pre-set sequence of system sequence calibration bits.

In order to enable the MPR function, it is necessary to write 1 in the A2 bit of Mrs's register MR3, and all the banks of DDR3 need to be in idle state before this;

Once MPR is enabled, any rd and RDA commands are introduced into the MPR register, and when the MPR register is enabled,

Unless MPR is banned (MR3 a2=0), only Rd and RDA are allowed. The reset function is allowed when MPR is enabled.

Precharge Power Down:bank is turned off after the in-progress command

Active Power Down:bank is still open after the in-progress command

Idle: All banks must be pre-charged, all timing is met, DRAM's ODT resistor, RTT must be high impedance.

Cwl:cas Write Latency. In a clock cycle, the internal write command and the time delay of the first input data, the unit is always an integer.

During the operation, all write-delay WL is defined as Al (Additive Latency) +cwl.

Rtt:dynamic ODT. New features introduced by DDR3. For better signal integrity on the data bus in a specific application environment,

You can change the end strength (or end-of-match) without the need for a specific Mrs command. The A9 and A10 bits in the MR2 are set RTT_WR. In DDR3,

There are two kinds of RTT values that can be selected, one is Rtt_nom, the other is RTT_WR; Rtt_nom is chosen when no command is written,

When the command is written, the ODT becomes RTT_WR, and when the command is finished, it returns to Rtt_nom. That is, the RTT appears after the ODT is enabled,

When there is no data on the bus, the RTT value is Rtt_nom, and when the data is available on the bus, the value of the ODT at this time is RTT_WR.

The specific DDR3 of the ODT generation sequence is shown in Figure 2. When the ODT is enabled, it is necessary to maintain a high-level ODTH4 clock cycle to be effective;

If the write command is placed in the register and the ODT is high, then the ODT must remain ODTH4 or ODTH8 so that the ODT can be effective.

ACT = ACTIVATE PREA = precharge all SRX = self-Refresh Eject

MPR = multi-use register READ = Rd,rds4,rds8 write=wr,wrs4,wrs8

mrs= Mode register set READ ap=rdap,rdaps4,rdaps8 write=wrap,wraps4,wraps8

Pde= power down into Ref=refresh zqcl=zq LONG calibration

Pdx= power off launches reset= start-up reset process Zacs=za short calibtation

Pre= pre-charge sre= self-refresh entry

4. Working principle

After describing some of the basic concepts described above, it is possible to make a basic description of how the DDR3 works in Figure 1 is understood.

First of all, the chip into the power, at the minimum of 200us of the power level, wait for 500usCKE to enable,

During this time the state initialization of the chip is initiated, and the process is independent of the external clock. Before the clock enable signal (CKE),

You must maintain a minimum of 10ns or 5 clock cycles, in addition to the need for a NOP command or deselect command to appear in front of the cke.

The DDR3 then begins the process of the ODT, and the ODT is always high-impedance before the reset and Cke are effective.

After the Cke is high, wait for txpr (minimum reset cke time), and then start reading the mode register from Mrs.

Then load the MR2, MR3 registers to configure the application settings, then enable the DLL, and reset the DLL.

Then, start the ZQCL command to start the ZQ calibration process. After the calibration is finished, the DDR3 is in a state of normal operation.

For the basic configuration process, it will now be over. The following, combined with the CH1 controller FPGA, describes the DDR3-related configuration.

Mrs can set the mode register value in the table above

Consider the example cs#,ras#,cas#,we# as L,l,h,h. The command is Row/bank Active; then cs#, command is invalid,

In the 4th clock cycle these 4 signals become l,h,l,h, the control table, the command read, after several clock cycle delay, after 3CLK reading data.

5. Basic functions

The DDR3 SDRAM is a high-speed dynamic random access memory with 8 banks in its internal configuration. The DDR3 SDRAM uses a 8n prefetch structure for high-speed operation. The 8n prefetch structure is combined with the interface to complete the transmission of two data words per clock on the I/O pin. DDR3 SDRAM a single read or write operation consists of two parts: one is the 8n bit width four clock data transmission in the internal DRAM core, the other is two corresponding n-bit wide, half clock cycle data transmission on the I/O foot.

The read and write operation of DDR3 SDRAM is a directional burst operation, starting from a selected position, the burst length is 8 or a chopped burst mode with the length of the programming sequence of 4. The operation starts with the active command, followed by a read/write command. The active command concurrently contains the address bits to select the Bank and row address (BA0-BA2 Select Bank, A0-A15 select Row). The Read/write command concurrently contains the starting column address with the burst operation and determines whether to publish the automatic pre-Charge command (via A10) and select BC4 or BL8 mode (via A12) (if the mode register is enabled).

Before normal operation, DDR3 SDRAM must be power-up and initialized in a pre-defined manner.

drivers for introducing DDR3 memoryAt present, DDR2 has not completely replaced the DDR memory, in the current machine environment, DDR2 Basic can meet the needs of various types of computer applications, then the latest generation of DDR3 compared to DDR2 advantages, 　　So that many of the world's top manufacturers, including Intel and AMD and A-data, are committed to DDR3 development and application? The main reason is that, since the DDR2 data transmission frequency to 800MHz, its core operating frequency has reached 200MHz, so it is difficult to upgrade upward, it is necessary to use new technology to ensure the speed of sustainable development. In addition, because of the speed increase, memory address/command and control bus need to have a new topology structure, and the industry also requires lower memory consumption. CPU Manufacturer's DDR3 memory RaidersIntel plans to add DDR3 memory support for its chipset in the middle of next year. 　　Malinowski, general manager of Intel Chipset division, said that by then the market would be ready to accept DDR3 memory. 　　Intel's newest 965 chipset family only supports DDR2 and gives up support for DDR. AMD is much more aggressive, and in contrast to the ambiguous memory of DDR2 in the year, obviously with the AM2 platform CPU in DDR2 memory performance is not satisfactory: to show the AMD CPU from the DDR platform to the DDR2 platform advantages, 　　Its demand for DDR2 memory frequency increases more than Intel Core, but at this stage in the DDR2 533/667-based memory market, the AM2 CPU is more constrained by the Gao Shiyan of DDR2 memory rather than the high frequency of DDR2 memory. AMD plans to fully import support for DDR3 memory in the next generation of k8l architecture CPUs. 　　In the AMD Roadmap, the K8L CPU will support simultaneous DDR2 and DDR3 memory, but it is clear that DDR2 memory is not the best choice for AMD, and that high-frequency, low-timing DDR3 memory will inevitably be an active target for AMD. At the same time, increased support for DDR3 memory also allows AMD to improve its passive position in the competition with Intel. the development of DDR3 memoryAs early as June 28, 2002, JEDEC announced the beginning of the development of DDR3 memory standards, but from the current situation, DDR2 just started to popularize, DDR3 standard is Lian Ying also did not see. However, there are many manufacturers have come up with their own DDR3 solutions, have announced the success of the development of DDR3 memory chips, from which we feel as if the DDR3 approaching footsteps. 　　The standard design work of DDR3 has come to an end, from the point that a chip can be produced. isuppli, the semiconductor market research agency, predicts that DDR3 memory will replace DDR2 as the dominant product in the market in 2008, and Isuppli believes that at that time DDR3 's market share will reach 55%. However, in terms of specific design, DDR3 and DDR2 's infrastructure is not fundamentally different. 　　From a certain point of view, the DDR3 is to solve the limitations of the development of DDR2 and the product of the birth. Due to the various shortcomings of DDR2 memory, restricting its further widespread application, DDR3 memory appears, is precisely in order to solve the problem of DDR2 memory, specifically: higher external data transfer rate more advanced address/command and control bus topology to ensure performance while reducing energy consumption in order to meet these　　requirements, the main improvements made on the basis of the presence of DDR2 memory in the DDR3 include: 8bit prefetch design, DDR2 for 4bit prefetching, so that the core frequency of the DRAM cores is only 100MHz of 1/8,ddr3-800 of the interface frequency. 　　Use the point-to-point topology architecture to mitigate the burden of address/command and control bus. With a production process below 100nm, the operating voltage is reduced from 1.8V to 1.5V, and the asynchronous reset (reset) and ZQ calibration functions are added. DDR3 Memory EncapsulationFrom the specifications, DDR3 will still follow the FBGA package, so in production and DDR2 memory is not very different. 　　But from a design point of view, because the DDR3 takeoff frequency at 1066MHz, which in the circuit layout will be a major challenge, especially the electromagnetic interference, it will also be reflected on the PCB to increase the cost of the module. It is expected that at the beginning of the DDR3 market, the price will be a major impediment, and with the gradual popularization, the increase in production can further reduce costs.
technical improvements to DDR3 memorySo, from the perspective of technology, DDR3 memory compared with the current mainstream DDR2 memory, its characteristics reflected in what aspects? We first introduce DDR3 memory for the shortcomings of the DDR2 in the improvement Logical Bank NumberThe 4Bank and 8Bank designs in the DDR2 SDRAM are designed to meet the needs of future large-capacity chips. DDR3 is likely to start with a 2Gb capacity, so the logical bank starts at 8, and is ready for the next 16 logical banks. Package (Packages)DDR3 due to the addition of some features, so there will be an increase in the pin, 8bit chip with 78 ball FBGA package, 16bit chip with 96 ball FBGA package, and DDR2 60/68/84 ball FBGA package three kinds of specifications. And the DDR3 must be in a green package and not contain any harmful substances. burst lengths (bl,burst length)Since the DDR3 prefetch is 8bit, the burst transmission cycle (Bl,burst Length) is fixed to 8, and bl=4 is also commonly used for systems DDR2 and early DDR architectures, DDR3 This adds a 4-bit Burst Chop (abrupt mutation) mode, That is, a bl=4 read operation plus a bl=4 write operation to synthesize a bl=8 data burst, which can be controlled by the A12 address line to control this burst mode. Also, it should be noted that any burst operations will be banned in DDR3 memory and not supported and replaced by more flexible burst control (such as 4bit sequential bursts). addressing Timing (Timing)Just as the DDR2 changes from DDR and the number of delay cycles increases, the CL cycle of DDR3 will be higher than DDR2. The CL range of the DDR2 is typically between 2 and 5, while the DDR3 is between 5 and 11, and the design of the additional delay (AL) also varies. DDR2 the range of Al is 0 to 4, while DDR3 Al has three options, 0, CL-1, and CL-2, respectively. In addition, DDR3 adds a new timing parameter-write delay (CWD), which depends on the specific operating frequency. new features for DDR3 memoryIf the previous section describes the DDR3 memory to DDR2 memory improvements more is a certain degree of correction or simple improvement, DDR3 memory and some DDR2 memory does not have the function, it is these, let DDR3 memory performance has a fundamental improvement Reset (reset)Resetting is an important new feature of DDR3, and a PIN has been specifically prepared for this purpose. The DRAM industry has long demanded this function, and it is now finally being implemented in DDR3. This pin will make the initialization of the DDR3 simple. When the reset command is in effect, DDR3 memory stops all operations and switches to the minimum active state to conserve power. During reset, DDR3 memory shuts down most of the functionality inside, so that both the data reception and the transmitter are closed. All internal program devices will be reset, the DLL (Delay phase-locked loop) and the clock circuit will stop working, and ignore any movement on the data bus. This will enable the DDR3 to achieve the most economical power. ZQ CalibrationThe ZQ is also a new foot, which is connected to a 240 ohm low tolerance reference resistor on this pin. This pin is automatically calibrated with the on-chip calibration engine (Odce,on-die calibration engine) through a command set to verify the data output driver on resistance and the end resistance value of the ODT. When the system issues this instruction, the on resistance and the ODT resistor are recalibrated with the corresponding clock cycle (512 clock cycles after power-up and initialization, with 256 clock cycles after exiting the self-flush operation, and 64 clock cycles in other cases). The reference voltage is divided into twoThe reference voltage signal Vref, which is very important for the memory system to work, will be divided into two signals in the DDR3 system. One is for the command and address signal Service VREFCA, and another for the data bus service VREFDQ, it will effectively improve the signal-to-noise level of the system data bus. automatic self-refresh according to temperature (Srt,self-refresh temperature)To ensure that the saved data is not lost, the DRAM must be refreshed periodically, and DDR3 is no exception. However, for maximum power savings, the DDR3 uses a new automatic self-refresh design (asr,automatic Self-refresh). When ASR is started, the frequency of the refresh is controlled by a temperature sensor that is built into the DRAM chip, because the frequency of the refresh is high, and the temperature increases. and the temperature sensor in the case of ensuring that the data is not lost, to minimize the refresh rate, reduce the operating temperature. However, DDR3 ASR is an optional design and does not necessarily support this feature on the market for DDR3 memory, so there is an additional feature that is the self-flushing temperature range (Srt,self-refresh temperature). With the mode register, two temperature ranges can be selected, one is the normal temperature range (e.g. 0 ℃ to 85 ℃) and the other is the extended temperature range, e.g. up to 95 ℃. For these two temperature ranges set within the DRAM, the DRAM will be refreshed at a constant frequency and current. Local Self-refresh (rasr,partial Array Self-refresh)This is an option for DDR3, which allows the DDR3 memory chip to refresh only a portion of the logical bank, rather than all of them, thereby minimizing the power consumption generated by self-flushing. This is similar to the design of mobile DRAM. Point-to-point connection (P2p,point-to-point)This is an important change to improve system performance and is a key differentiator from the DDR2 system. In a DDR3 system, a memory controller will only deal with one memory channel, and this memory channel can only be one slot. So the memory controller and the DDR3 memory module is a point-to-point (p2p,point-to-point) relationship (single-Physical bank module), or a point-to-point (p22p,point-to-two-point) relationship (dual-physical bank module), This greatly reduces the load on the address/command/control and data bus. In the memory module, similar to the DDR2 category, there are standard DIMM (desktop PC), So-dimm/micro-dimm (notebook), fb-dimm2 (server) points, The second-generation FB-DIMM will use a higher-spec AMB2 (advanced memory buffer). 　　However, the current standard-setting work on DDR3 memory modules has just begun and the pin design has not been finalized. In addition, DDR3 also has a lot of new designs in power management, multi-purpose registers.

"Turn" DDR3 detailed (Take micron MT41J128M8 1Gb DDR3 SDRAM as an example)