"Turn" talking about DC/AC scan test

SCANTechnology, i.e.ATPGTechnology--TestStd-logic,The main implementation tool is: GenerateATPGUseMentorOfTestkompressAndSynopsys Tetramax; insertScan ChainMain useSynopsysOfDFT compilerNormally, what we call Dcscan is the normal scan test , which is the slow test, the test frequency is 10m-30m, and the AC scan is the at-speed scan . That is, the real-speed test, the test frequency and chip real operating frequency is the same. 70Age to1995During this period of time, because the chip is operating at a low frequency, only20-100m，ScanTest onlyDC SCAN, we'll be able to capture allStd-logicManufacturing defects. But1995Years later, test scientists and engineers found thatDC SCANIt can be problematic to test for non-defective chips that are used at high operating frequencies. The fundamental reason is that as the manufacturing process moves deep into the submicron, the working frequency of the chip is increased to 200m-1g, and the original SCAN test method and model can no longer capture all the std-logic manufacturing flaws. The consensus is that -"Run, scan," and increase the frequency of the scan to match the true operating frequency of the chip, while using the new Transition ATPG model To produce the test pattern.

Below we introduce The similarities and differences between DC Scan and AC scan

Today's high-speed chips for industrial production require DC scan testing and AC scan testing, so DFT engineers also have to plug in two test circuits, producing two sets of test patterns.

The specific implementation process is as follows

1 read into a web table without inserting a scan

2 Insert the scan chain and OCC (on chipclocking) modules using design compiler , while inserting the MUX, fix DRC

3 using testcompress to implement EDT compression scan chain

4 use testcompress to generate test Dc/acpattern, while generating test validation testbench

5 Verifying The correctness of the dc/ac patterns and the correctness of the circuit

6 use SDF to verify that the timing of the dc/acpatterns-related circuitry meets the requirements

7 Use Dc/ac patterns (wgl file) to convert to ate required format, Debug and use on ate

the ATPG tool uses transition Faultmodel such as

The common OCC circuit structure is as follows

We typically insert a circuit after the OCC like

So the Dc/ac SCAN test, Kevin He here, ask friends to speak freely.

Problem

1) Why is the AC scan more pattern than the DC scan test ?

2) How does AC SCAN get a fast clock?

3) What problems should the AC SCAN pay attention to during ate commissioning?

"Turn" talking about DC/AC scan test