R6 STM32 I2C-read/write EEPROM, r6stm32i2ceeprom

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Author: User

R6 STM32 I2C-read/write EEPROM, r6stm32i2ceeprom

STM32 I2C-read/write EEPROM

Due to its few pins, the I2C communication protocol features simple hardware implementation and high scalability, and does not require external transceiver devices for communication protocols such as USART and CAN, it is now widely used for communication between multiple IC in the system.

I2C Physical Layer

It is a bus supporting multiple devices. "Bus" refers to the signal line shared by multiple devices. In an I2C communication bus, multiple I2C communication devices can be connected to multiple communication hosts and multiple communication slaves.

An I2C bus uses only two bus lines, one bidirectional serial data line (SDA) and one serial clock line (SCL ). A data line is used to represent data, and a clock line is used to send and receive data for synchronization.

Each device connected to the bus has an independent address, which can be used by the host to access different devices.

I2C protocol layer

Basic read/write process

Host write data to slave:

The Host reads data from the slave:

Composite communication format:

Start and Stop Signals of communication

The SDA line switches from the high level to the low level during high-power period.

The SDA line switches from the low level to the High Level in high-power mode, indicating that the communication is stopped.

The start and stop signals are generally generated by the host.

Data Validity (data verification)

I2C uses the SDA signal line to transmit data and the SCL signal line to synchronize data. The SDA data line transmits one bit of data in each clock cycle of the SCL.

The SDA indicates that the data is valid when the SCL is high. That is, when the SDA is high, the data is "1", and when the SDA is low, the data is "0 ".

When the SCL is low, the SDA data is invalid. Generally, SDA performs a level switch to prepare the data for the next time.

Address and data direction

Each device on the I2C bus has its own independent address. When the host initiates a communication, it uses the SDA signal line to send the device address (SLAVE_ADDRESS) to find the slave. The device address can be 7 or 10 characters.

A Data bit R/W that follows the device address is used to indicate the data transmission direction. When the data direction bit is "1", it indicates that the Host reads data from the slave machine, when the bit is "0", it indicates that the host writes data to the slave machine.

One byte and eight data bits

Seven-digit data device address + 1/0 = eight-digit data read/write address

I2C diagram of STM32

I2C features and architecture of STM32

Software Simulation Protocol: Use the CPU to directly control the level of the Communication pin to generate a logic that complies with the communication protocol standards.

Hardware Implementation Protocol: the I2C chip peripherals of STM32 are responsible for implementing the I2C communication protocol. As long as the peripheral is configured, it will automatically generate communication signals according to the Protocol requirements, send and receive data and cache it. The CPU can send and receive data as long as it detects the status of the peripheral and the access data register. This hardware peripherals process I2C protocols to reduce CPU work and simplify software design.

** Function: ** the I2C peripherals of STM32 can be used as the communication host and slave, and support 100 Kbit/s and 400 Kbit/s speeds.

Rate, supports 7-bit and 10-bit device addresses, supports DMA data transmission, and has the data verification function.

1 Communication pin

2. Clock Control Logic

3. Data Control Logic

4 Overall control logic

Communication pin

All the hardware architectures of I 2 C are expanded based on the left-side check boxes and SDA lines in the figure (the SMBA lines are used for warning signals of SMBUS and I2C communication is not used ). The STM32 chip has multiple I2C peripherals, and their I2C communication signals are routed to different GPIO pins. These specified pins must be configured for use.

Clock Control Logic

The clock signal of the SCL line is controlled by the I 2 C interface according to the clock control register (CR). The control parameter is mainly the clock frequency. You can modify the parameters related to the communication rate by configuring the I2C Cr register:

 You can select the standard/fast mode for I2C communication. The two modes are I2C and correspond to the communication rate of 100/400 Kbit/s respectively.

In quick mode, you can select the duty cycle of the SCL clock. You can select Tlow/Thigh = 2 or Tlow/Thigh = 16/9 mode. We know that the I2C protocol samples the SDA signal during high-power period of the SCL, in the case of low-power-of-check, SDA prepares the next data. Modifying the High-Level ratio of the model affects data sampling. However, the ratio difference between the two modes is not significant. If not, the requirements are very strict, you can just select it here.

The  Cr register also has a 12-bit configuration factor, which works together with the input clock source of I2C peripherals to generate the SCL clock. the I2C peripherals of STM32 are mounted on the APB1 bus, when PCLK1 is used as the clock source of APB1, the output clock formula of the SCL signal line is as follows:

The calculation result shows that the CR is 30. Writing this value to the Register bit can control the IIC communication rate to 400 KHz. In fact, even if the configured SCL clock is not completely equal to the standard 400 KHz, the correctness of IIC communication will not be affected, because all data communication is coordinated by the SCL, as long as its clock frequency is not far higher than the standard.

Data Control Logic

The I2C SDA signal is mainly connected to the Data shift register. The data source and target of the Data shift register are the data register (DR), the address register (OAR), the PEC register, and the SDA data line. When sending data externally, the Data shift register uses the "data register" as the data source to send data one by one through the SDA signal line. When receiving data from outside, the Data shift register stores the data sampled by the SDA signal line one by one in the "data register. If data verification is enabled, the received data is computed by the PCE calculator and the calculation results are stored in the "PEC register. When the I2C of STM32 works in slave mode and receives the device address signal, the Data shift register compares the received address with the value of STM32's own "I2C Address Register" to respond to host addressing. You can modify the I2C address of STM32 by modifying its own address register. You can use two I2C device addresses, which are stored in OAR1 and oar2.

Overall control logic

The overall control logic is responsible for coordinating the entire I2C peripherals. The operating mode of the control logic changes according to the parameters of the configured "control register (CR1/CR2. When the peripherals work, the control logic modifies the "status registers (SR1 and SR2)" according to the working status of the peripherals. We only need to read the register bit related to these registers, you can understand the I2C working status. In addition, the control logic also controls the generation of I2C interrupt signals, DMA requests, and various I2C communication signals (starting, stopping, and responding signals) as required ).

Communication Process

When I2C peripherals are used for communication, it writes parameters to different data bits in the "Status Register (SR1 and SR2)" at different stages of communication. We can read these register marks to understand the communication status.

Main Transmitter

The figure shows the "main transmitter" process, that is, the process of sending data to the outside when the host is used as the I2C communication.

If I2C interrupt is enabled, the I2C interrupt signal will be generated when all the above events are generated. After the I2C interrupt service program is executed, check the register bit to determine which event it is.

Master Receiver

The process of receiving data from the outside when the master receiver is used as the host for I2C communication

In the process of sending and receiving, some events not only mark the status bit we mentioned above, but also indicate the status bit such as the host status, it is complicated to clear the flag after reading. We can use the STM32 standard library function to directly detect the composite flag of these events to reduce programming difficulty.

Detailed description of I2C initialization struct

The STM32 Standard Library provides I2C initialization struct and initialization functions to configure I2C peripherals. The initialization struct and function are defined in the library file "stm32f10x_i2c.h" and "stm32f10x_i2c.c.

// I2C initialization struct typedef struct {uint32_t I2C_ClockSpeed ;/*! <Sets the SCL clock frequency. The value must be lower than 400000 */uint16_t I2C_Mode ;/*! <Specified working mode: I2C mode and SMBUS mode */uint16_t I2C_DutyCycle;/* specify the clock duty cycle. Optional values: low/high = and 16: 9 */uint16_t I2C_OwnAddress1 ;/*! <Specify the I2C device address */uint16_t I2C_Ack ;/*! <Enable or disable the response (usually enable) */uint16_t I2C_AcknowledgedAddress ;/*! <Length of the specified address, which can be 7 and 10 digits */} I2C_InitTypeDef;

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