Realization of S5PV210 Development Series three _ Simple bootloader

s5pv210 Development Series three the realization of simple bootloader

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Bootloader is the code that executes the first segment of the embedded system after power-on. For a simple processor, there may not be a concept of bootloader, but for the application processor, there are different boot methods, different storage devices (Nand Flash, SD/MMC, DDR2, SRAM, etc.), different operating systems, etc., Often requires a bootloader first initialize the CPU and related hardware, establish a memory space mapping, load the kernel or application into the appropriate memory execution location, finally call the kernel or application, release the CPU control, complete the entire bootloader process. The author here makes a brief introduction to the bootloader realization of s5pv210. 1. Bootloader Process

Bootloader is heavily dependent on the implementation of the specific hardware, the same CPU core architecture, different manufacturers of processors produced by the bootloader are not the same, even for the same CPU, the board of different hardware configurations, are often targeted to achieve its bootloader. Therefore, bootloader functions, processes, and so on have no specific requirements, as long as the system's hardware and software environment to a suitable state, and ultimately the operating system kernel or application to prepare the right environment. Generally, two different modes of operation should be implemented for a bootloader: Boot load mode and download mode. The boot load mode is bootloader the operating system or application into RAM from a solid state store in the device system, which is the normal mode of bootloader after the device has been molded, without the user's intervention. Download mode is bootloader can be through the serial port, USB or network communication means to download files from the host, and eventually write to a device system of a solid-state storage, this mode used in the device development debugging, for the brush machine upgrade. Here the author from his point of view simple introduction bootloader implementation of the general process.

The code files associated with bootloader are placed in the System directory folder with the following directory schema:

S5PV210.S, start code file, code execution of the entrance, control the entire bootloader execution process, finally set up the C run environment, into the application main entrance.   LOWLEVELINIT.S, board-level initialization code, including initialization of CPU clocks, DDR2 memory controller initialization, Code load implementation (SD/MMC card boot, Nand flash boot).   COPROCESSOR.C, coprocessor-related code, mainly CP15 coprocessor L1 cache, L2 cache, MMU memory mapping, interrupt vector base address and other operating code.   NANDBOOT.C, to implement NAND flash boot-related NAND driver code, to achieve the corresponding NAND code download, NAND code start interface implementation.   DOWNLOAD.C, implement code download debugging function, support code to download memory debug run directly, support code download into NAND flash, support uboot memory download run Debug and NAND download cure.   EXCEPTION.C, exception handling related code, support the complete architecture of interrupt processing, such as interrupt nesting processing, interrupt registration, interrupt opening and other interface implementations, for the System Application architecture implementation.   RETARGE.C, the underlying redirection of standard IO, supports standard IO functions in C libraries, such as standard input, output stream redirection to the serial port, file operation redirection to the corresponding file system interface implementation, etc., for the System Application architecture implementation. S5pv210.icf,iar a link file to specify the layout of the onboard memory range, code, and RAM.

Here the author explains that before the establishment of the C run environment before the bootloader code are address-independent, the CPU power will load a portion of the bootloader code to the internal RAM execution, any RAM address this part of the bootloader should be able to execute correctly. Do not attempt to invoke C library functions in bootloader, note that the C code C run environment in bootloader is not valid. In Bootloader, the most critical hardware environment should be initialized, and other non-critical hardware initialization or function code can be placed in the C run environment after the establishment of processing. 1.1. Exception Vector Table

When an exception occurs, the arm core takes the corresponding exception vector address from the exception vector table, and an IRQ interrupt obtains the IRQ exception vector address from the 0x18 offset of the exception vector table. The exception vector table is used to record the location of code handling when each exception enters. In addition to the CORTEX-M processor with nested vector interrupt controllers (NVIC), the following exception vector processing is established for all series of arm cores.

Arm

__iar_program_start

BLX Reset_handler

LDR PC, Undef_addr

LDR PC, Swi_addr

LDR PC, Pabt_addr

LDR PC, Dabt_addr

LDR PC, Notuse_addr

LDR PC, Irq_addr

LDR PC, Fiq_addr

DCD 0X55AA55AA; The 0x20 location is used to determine the area where the code runs

Undef_addr

DCD Undef_handler

Swi_addr

DCD Swi_handler

Pabt_addr

DCD Pabt_handler

Dabt_addr

DCD Dabt_handler

Notuse_addr

DCD 0; Reserved Address

Irq_addr

DCD Irq_savecontext

Fiq_addr

DCD Fiq_handler

Irq_savecontext

; Save interrupt context, support interrupt nesting

SUB LR, LR, #4; Calculate return Address

Stmfd sp!,{r0-r12, LR}; All registers are pressed to save

MRS R0, SPSR; Save the CPSR before the break (that is, the current SPSR)

Stmfd sp!, {R0};

MSR cpsr_cxsf, #Mode_SYS +i_bit; Switch to System mode

Stmfd sp!, {LR}; Pressure stack system mode LR

LDR R0, =irq_handler; IRQ code handling in System mode

BLX R0; Call Interrupt handler function

Ldmfd sp!, {LR}; Out-of-stack system mode LR

MSR cpsr_cxsf, #Mode_IRQ +i_bit; Switch to IRQ mode

Ldmfd sp!, {R0}; Returns the CPSR before the break

MSR spsr_cxsf, R0

Ldmfd sp!, {r0-r12, pc}^; ^ table restored from SPSR to CPSR

Pubweak Undef_handler

Pubweak Swi_handler

Pubweak Pabt_handler

Pubweak Dabt_handler

Pubweak Irq_handler

Pubweak Fiq_handler

Undef_handler

Swi_handler

Pabt_handler

Dabt_handler

Irq_handler

Fiq_handler

B. 1.2. Off-guard Dog

The first thing to do in the reset code is to turn off the watchdog, because if the watchdog is turned on, it is not possible to feed the dog during initialization of the boot code, which can cause the processor to reset continuously.

; Watchdog off

LDR R0, =wt_base

LDR R1, =0

STR R1, [R0] 1.3. Turn off all interrupts

When the startup code is not completed, the individual states are not determined, and if there is an interrupt open and cause an interrupt exception, the code may run.

; Turn off all peripheral interrupts

LDR R1,=0XFFFFFFFF

LDR R0,=vic0_base

STR R1,[r0, #INT_EN_CLR_OFS]

LDR R0,=vic1_base

STR R1,[r0, #INT_EN_CLR_OFS]

LDR R0,=vic2_base

STR R1,[r0, #INT_EN_CLR_OFS]

LDR R0,=vic3_base

STR r1,[r0, #INT_EN_CLR_OFS] 1.4. Initializing the coprocessor

The ARM core supports up to 16 coprocessors, which typically include the CP14 debug communication coprocessor and the CP15 system control coprocessor. In bootloader, the actual register physical address needs to be initialized to read and write, so the CP15 coprocessor should be initialized to close the cache, close the MMU, set the interrupt vector table base, and so on.

; Initializing the coprocessor

EXTERN Coprocessor_init

BLX coprocessor_init 1.5. Initializing the system clock

In general, after the processor is reset, it is run at a lower speed clock, and the processor's individual clocks are usually set as fast as possible to speed up the boot.

; System Clock Settings

EXTERN Clock_init

BLX clock_init 1.6. Initializing external memory

In addition to nor Flash can directly execute the code, other code memory such as NAND flash, SD/MMC are not directly execute code. Typically, the code is executed after loading into RAM for the application processor.

; External Memory Control settings

EXTERN Eram_init

BLX Eram_init

LDR SP,=SFE (Cstack); After RAM initialization, adjust the stack pointer to external RAM 1.7. Download Mode

In the debugging development phase, you can download the code directly to the Ram debug execution, avoid repeatedly burning solid state memory, speed up debugging and development, after determining the code OK, then download the code into the Solid state memory (Nandflash). After development is complete, the download mode code can be commented out.

; Check whether to enter the serial download mode, press and hold the SPACEBAR to enter the serial download mode

Extweak Downloadcheck

BLX downloadcheck 1.8. Code Loading

For storage where code is stored in NAND flash, SD/MMC, etc. that cannot execute code directly, bootloader is required to read the user code from these devices into specific memory. And for the memory that nor flash can execute code directly, usually in order to improve performance, it will also read the code from nor flash, in memory execution.

; Copy user code to RAM

EXTERN Copycodetoram

BLX Copycodetoram 1.9. MMU Memory Map

In order to improve the CPU processing performance, the MMU must be open, before opening, you need to establish the corresponding memory space mapping table, set the corresponding memory area access rights, and so on. After opening the MMU, you must also open the L1 i/d cache, L2 cache, Hardware branch prediction function, otherwise the performance of the CPU will be extremely low, there are dozens of times times the performance difference.

; MMU initialization

EXTERN Mmu_init

BLX mmu_init 1.10. Initialize Stack

The arm core has a variety of operating modes, each of which must be assigned and initialized so that the code can be executed correctly in the appropriate mode.

; Stack initialization

; Enter Undefined instruction Mode and set Itsstack Pointer

LDR R0,=SFE (Und_stack)

LDR R1,=mode_und+i_bit+f_bit

MSR CPSR_C,R1

MOV sp,r0

; Enter Abort Mode and set its Stack Pointer

LDR R0,=SFE (Abt_stack)

LDR R1,=mode_abt+i_bit+f_bit

MSR CPSR_C,R1

MOV sp,r0

; Enter FIQ Mode and set its Stack Pointer

LDR R0,=SFE (Fiq_stack)

LDR R1,=mode_fiq+i_bit+f_bit

MSR CPSR_C,R1

MOV sp,r0

; Enter IRQ Mode and set its Stack Pointer

LDR R0,=SFE (Irq_stack)

LDR R1,=mode_irq+i_bit+f_bit

MSR CPSR_C,R1

MOV sp,r0

; Enter Supervisor Mode and set its stackpointer

LDR R0,=SFE (Svc_stack)

LDR R1,=mode_svc+i_bit+f_bit

MSR CPSR_C,R1

MOV sp,r0

; Enter System Mode and set its Stack Pointer

LDR R0,=SFE (Cstack)

LDR R1,=mode_sys

MSR CPSR_C,R1

MOV sp,r0 1.11. Initializing the C operating environment

Before entering the C portal, you need to initialize the C environment, such as clear 0 global variables, static variable areas, etc. Here the compiler's library function __cmain to complete the initialization of the C environment, and finally the real application Portal main function, with an absolute address jump to the C portal __cmain,bootloader release the CPU control, complete the process.

; Initialize VFP (ifneeded).

EXTERN __IAR_INIT_VFP

LDR R0,=__IAR_INIT_VFP

BLX R0

; Continue to Mainfor c-level initialization.

EXTERN __cmain

LDR R0,=__cmain

BX R0 2. Code Burn-Write

The code can be stored in NAND flash or SD/MMC card, the code is generally written into the SD/MMC card, so that no complicated operation and expensive burner and so on. SD/MMC card after booting through the inside of the bootloader download function to download the corresponding code on the host device to the NAND flash, then no longer with the SD/MMC card, set NAND flash boot, The code update can also be downloaded via bootloader on Nandflash.

SD/MMC Card Start-up requires dedicated burning software Sdboot,sdboot.exe for the author under Windows for the Samsung s3c2416 and s5pv210 two platforms developed SD/MMC start burning tool. SD/MMC boot requires the corresponding code format and needs to be burned into the SD/MMC card specified location, SdBoot.exe tool Set code format conversion and SD/MMC card burning in one, Can burn s3c2416 and s5pv210 two platform under the author of the bare metal bootloader,wince bootloader,uboot, tools easy to use.

Figure 2-1 SdBoot.exe Tool 3. bootloader Download Function

Bootloader through the serial port to achieve the host code file download, host-side code download needs Samsung tools Dnw.exe tools, connect a good serial port, press and hold the space bar, the target board power will enter the bootloader download mode.

Figure 3-1 bootloader Download mode

Where option 1 can be based on the application developed by the author bootloader, download into RAM, and directly debug the run. The code that is downloaded into RAM is the code compiled directly by the compiler and is not converted by the Sdboot tool format.

Option 2 for Uboot debugging development, you can directly download the compiled uboot binary code into RAM, and directly debug the run.

Option 3 is used for code burning into NAND flash, the conversion through the Sdboot tool format based on the author bootloader application code, uboot code downloaded into NAND flash, then set NAND flash boot. 4. bootloader function

The author of the s5pv210 bootloader set the highest CPU frequency 1ghz,mmu 1:1 memory space linear mapping, and open L1 i/d cache, L2 cache, Hardware branch prediction function, so that the CPU can achieve maximum throughput performance. Initialize memory, be able to recognize SD/MMC boot and NAND flash boot, automatically load application code to RAM location. A unified interrupt management architecture and redirection of underlying IO operations can be more focused on application development. 5. Appendix

Bootloader.rar,bootloader under IAR test Engineering and sdboot tools.

Http://pan.baidu.com/s/18pFhs