Recording as you want (this book "Step by Step surprise"-software core processor internal design analysis "is recommended)

 

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Before I started working in a chip company, I knew very little about the chip design. I knew a lot about the chip company datasheet. There is no such resource, and there is no such requirement. However, when I came to a new company, especially after I realized the open-source CPU, everything had changed. Open-source CPU-based code, open-source code compilation tools, open-source iverilog, GTK wave analysis tools, as long as we have enough persistence and perseverance, you can modify and simulate the CPU Hardware code on your PC. This was previously impossible.

 

Currently, the most famous CPU in the opencore field is openrisc. In addition to the convenience of downloading code online, the Linux open-source community also supports it, at the same time, you can easily transplant it to the FPGA Development Board. Compared with the English documents, there are not many Chinese books in the open field in China. The software core processor internal design and analysis discussed in the title today is one of them. I have never met the author of a book, but objectively speaking, this book is really good.

 

The content of the book basically includes most of the openrisc code, which basically includes,

 

    （1）mmu    （2）cache    （3）qmem    （4）store buffer    （5）multiplier    （6）cpu pipeline， include if/ id/ exe/ ls/ wb    （7）tt、pm、pic    （8）soc    （9）wishbone bus

 

Of course, reading efficiency is still relatively low. If you have the opportunity, you can still use openrisc + toolchain + test.pdf + gtkwave to generate binfiles according to the link file requirements and store them in qmem. In this way, you can use the gtkwave tool to view various signals in the module at any time, it is very convenient to use.