We know that there are 27 external address lines (addr0 ~ Addr26), the corresponding access range is 128 M, in addition, the CPU also leads to eight chip selection signals (ngcs0 ~ Ngcs7) -- effective at low level, corresponding to eight banks, thus achieving 1 GB of address access space.
Theoretically, we know that the available address access range is 4 GB (32-bit CPU). What is the other address space used? One part is used as the internal register address of the CPU, and the other part is retained.
Note: The range of the S3C2440 registers is 0x48000000 ~ 0x5fffffff; the address of the storage controller is 0x48000000 ~ 0x48000030 (13 );
Bank1 ~ The bank5 connections are similar, so the corresponding register settings are the same. For more information, see
Setmem 0x48000008, 0x00002e50, 32
Setmem 0x4800000c, 0x00002e50, 32
Setmem 0x48000010, 0x00002e50, 32
Setmem 0x48000014, 0x00002e50, 32
Setmem 0x48000018, 0x00002e50, 32 is mainly used to set the access time series
Bank0 is slightly different. setmem 0x48000004, 0x00000f40, and 32 (I wonder if the timing settings are related to boot ROM)
Next we will focus on the analysis of the connection and addressing methods of SDRAM.
Several signals for SDRAM:
• The Clock effective signal scke of SDRAM;
• Clock signal sclk0/sclk1 of SDRAM;
• Data mask signal dqm0 ~ Dqm3, corresponding to nwbe;
• The nscs0 chip selection signal of SDRAM is the same as that of ngcs6;
• Select a pulse signal for the nsras line address;
• Select the pulse signal for the nscas column address;
First, SDRAM is composed of several storage arrays, each of which is a logical bank
Each logical bank is a storage array and is addressed by the row address and column address, just like an Excel document table. Generally, there are four logical banks.
Access to SDRAM is divided into the following steps;
• Enable the effective bank6 starting address of nscs0 for the chip selection signal to be 0x30000000;
• Select the corresponding logical Bank (addr25 addr24) and addr26? (THINKING)
• Unified row-column addressing for the selected chip (row address number: 13, column address number: 9) When nsras is valid, addr2 ~ The line address signal bit [] is sent on addr14. When nscas is valid, the line address signal bit [] is sent.
Why addr0 and addr1 are not connected. We know that bank6 is 32-bit wide, so these two address lines will not be used (always 0 );
The starting address of bank6 is 0x30000000, so the access address of SDRAM is 0x30000000 ~ 0x33ffffff.
• Once the storage unit is found, data transmission starts. How can we organize the 32-bit data?
The memory connection enables 8-bit access, 16-bit access, and 32-bit access.
The four signals nwbe3 ~ 0, which is the control of byte selection.
Access by 8 bits, that is, if the Code contains:
* (Unsigned char x *) 0x30000000 = 0x78;
It is a byte write, and only the nbwe0 signal is valid.
If it is 0x30000001, only nbwe1 is valid (low), and other values are invalid (high ).
For example, what if it is a 16-bit access?
For a 16-bit access, the code is generally:
* (Unsigned short *) 0x30000000 = 0x1978;
This is a 16-bit write. However, you must note that the priority bit must be 0 but not 1. For example, the address 0x30000001 may cause CPU exceptions because it must be 16-bit aligned!
Dat16 = * (unsigned short *) 0x30000002;
This is a 16-bit read
During a 16-bit access, nwbe1, 0 = low, nwbe3, and 2 = high in 0x30000000 address write operations. When 0x30000002, It is nwbe3, 2 is low, nwbe1, 0 is high (invalid)
The 32-bit value is 4-byte alignment, that is, the minimum two address bits A1, a0 must be 0, that is, for 32-bit access, 0x30000001, 0x30000002, 0x30000003 will cause an exception (error)
For 32-bit access, the next address of 0x30000000 is 0x30000004, because the address is a byte address, but the access to 0x30000000 ~ 0x30000003 four bytes, that is, nwbe3 ~ Four signals are responded together !!!
Different CPU access mechanisms are different. For details, refer to the Manual, which is selected separately.
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