(Reporter) What is the difference between the master and slave on the aveon bus? (SOC) (FPGA builder)

Abstract
Weekly slave is used most of the time, so I usually feel better about slave. If component is deployed, when should the master be established and when should the slave be established ?.

Introduction
In Jay Kraut's Hardware Edge Detection Using an Altera Stratix niosii Development Kit, the following statement breaks through the master and slave.

The Masters initiate communication and the Slave responds to them.

The next time you want to modify component, you can think about this sentence and let yourself know whether to restore the master or slave.

See also
(Formerly known as the benchmark) in-depth exploration of the checksum master slave instance (SOC) (FPGA builder) (nio ii) (de2) of Altera)

Reference
Jay Kraut 2006, hardware Edge Detection Using an Altera Stratix niosii developement kit, Dept. ECE, University of Manitoba