(Reporter) how to increase the number of Reg and wire that SignalTap II can detect? (SOC) (Quartus II) (SignalTap II)

Abstract
It cannot be detected in SignalTap II Reg and wire. It is mainly because of the Quartus II connector, Which is set in the Quartus II connector, you can increase the number that SignalTap II can detect.

Introduction
Use environment: US us II 8.0

In (original) How to Use SignalTap II to inspect Reg and wire values? In (SOC) (OpenGL) (Quartus II) (SignalTap II), I have used synthesis attribute encoding to specify that Quartus II will not normalize a Reg and wire, in order to facilitate SignalTap II observation, it is feasible, but the Code must be changed to its missing point. If you can configure it in Quartus II, reg and wire can be viewed in SignalTap II, which is more convenient than linear.

In using SignalTap II embedded logic analyzers in systems, p.3 of paper mentioned:

By turning off the incremental compilation Option , Pre-synthesis signals can be added to the SignalTap II Ela in the later sections. pre-synthesis signals exist after design elaboration but before any synthisis optimations are done. this set of signals shoshould reflect your register transfer level (RTL) signals.

Setting Method
Assignments-> Settings: Category: compilation process settings-> incremental compilation

See also
(Original) How to Use SignalTap II to check Reg and wire values? (SOC) (OpenGL) (Quartus II) (SignalTap II)

Reference
Using SignalTap II embedded logic analyzers in FPGA Builder systems