Reprinted PLL Working Mode Analysis

There are four working modes of PLL. Only by understanding the characteristics of these four working modes can we select the appropriate mode in the design to complete the expected functions designed by ourselves. The four working modes are normal mode, zero delay buffer mode, and non-compensation mode) source-synchronous mode ).

1. The relationship between the input clock and the output clock in normal mode is shown in.

 

In the figure, the first waveform is the PLL inclk, which is generally the output of the active crystal oscillator on the board and directly connected to the FPGA clock input pin. The second waveform is the PLL clock at the register clock port, it indicates the time clock processed by the PLL, that is, the C0 and C1 mentioned in the previous post. Generally, it is connected to the global clock network inside the FPGA, and generally cannot be obtained from the FPGA pin; the bottom waveform is external PLL clock outputs, that is, C2, which can be used by FPGA's internal global clock network or to pins for other devices other than FPGA.

The Common Mode features that C0 and C1 have no latency compared to the input clock (not marked in the figure), but C2 has a latency (marked as ).

2. Zero Delay buffer Mode)

In this mode, we can see that there is no delay between C2 and the input clock (not marked in the figure), but there is a delay between C0 and C1 (marked as B in the figure ). This work mode is the opposite of normal work mode.

3. Non-compensation mode (no compensation mode)

In this mode, for example, C0 and C1 have a small latency (marked as C in the figure) relative to the input clock, and C2 has a large latency (marked as D in the figure ).

4. Source-synchronous Mode)

In this mode, for example, the clock input to FPGA has a fixed phase relationship with the data input to FPGA (marked as E and F in the figure). After the PLL, the phase relationship remains unchanged, there is only a latency.