Research and Implementation of serial data communication between C6000 and c2000 series DSPs

Research and Implementation of serial data communication between C6000 and C2000 series DSPs

[Date: 2008-7-31]

Source: China Power Grid Author: Han kiliang, Zhang Tao

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TMS320C6711 is a 32-bit floating point DSP of TI's TMS320C6000 series. It features dedicated hardware logic CPU, In-chip memory, and in-chip peripherals. It supports independent or mixed programming of assembly and C language. The main feature of this series of DSPs is the use of the VLIW architecture. Therefore, multiple commands can be sent in a single cycle to achieve high command-level parallel efficiency. Its computing and processing speed is very fast, and the system's single command cycle can reach 6.67ns. It is widely used in DSL, wireless base stations, radar sonar, digital image processing, and other aspects. There are two multi-channel buffer serial interfaces (McBSP) in TMS320C6711. McBSP can be prepared not only as a serial interface, but also as a general input (GPI) and output (GPO) independently) and the input and output ports (GPIO ). The advantage is that the data processing capability is strong, but the control interfaces are few, the number of external devices integrated in the chip is small, and the control capability is weak.
TI's TMS320LF2407 is a 16-Bit fixed-point DSP microcontroller with embedded WDT, CAN bus controller, ADC, and serial peripheral interface (SPI) asynchronous Serial Port (SCI) and other peripheral modules, with a large number of input and output pins (GPIO), can meet the control requirements of the control system. However, due to the shortest speed of the command cycle of PostgreSQL is 25ns (40 MHz clock speed), the operation speed of Systems with extremely large data processing workload is slightly insufficient.
Most digital image processing application systems require the system to have powerful data processing capabilities to meet the real-time requirements for image processing, and require the system to have powerful control capabilities, to control a large number of external devices. In the actual application system, the real-time processing of digital images is completed by using TMS320C6711 as the processor, and the control function of the system is completed by using TMS320LF2407 as the controller, so that the system's data processing and external device control capabilities can be taken into account. This system requires an effective data exchange channel between TMS320C6711 and TMS320LF2407. The design concept described in this article is based on the above engineering needs.
1. System Structure
This system is an embedded digital image processing system, as shown in System Structure 1. The digital image data is processed by the lower computer TMS320C6711, and the processing result is transmitted to the upper computer by asynchronous serial communication. The upper computer, such as the analog quantity, switch quantity, and other parameters, the image processing result received through the asynchronous serial port is sent to the remote monitoring terminal through the CAN bus.

The multi-channel buffer serial interface McBSP of TMS320C6711 and the SCI module of postgresql support asynchronous digital communication in standard format through specific software and hardware designs. The communication data format is: A Start bit, data (length can be programmed in 16 bits ~ Optional), available odd/even/non-polar bits, one or two stop bits, as shown in figure 2.

1.1 McBSP Interface
Figure 3 of McBSP. McBSP can be divided into two parts: Data tunnel and control channel. The data transmission pin (dx) and the data receiving pin (DR) are responsible for data transmission and receiving, respectively, the clock sending pin (clkx) and the clock receiving pin (clkr) the transmission frame synchronization pin (FSX) and the receiving Frame Synchronization pin (FSR) provide serial clock and control signals. The CPU and DMA controller communicate with McBSP through the peripheral bus. When sending data, the CPU and DMA write the data into the data sending register (dxr1, dxr2), then copy the data to the sending shift register (xsr1, xsr2), and output the data to the DX pin by sending the shift register. Similarly, when receiving data, the data received on the Dr pin is first moved to the receiving shift register (rsr1, rsr2), then copied to the receiving buffer register (rbr1, rbr2 ), RBR then copies the data to the data receiving register (drr1, drr2) and notifies the CPU or DMA to read the data through serial port events. This multi-pole buffering method enables on-chip data communication and serial data communication to be performed simultaneously.

1.2 SCI interface
The SCI module supports communication between the CPU and other asynchronous devices in the standard format. It has two I/O pins: SCIRXD (Serial Data receiving end) and SCITXD (serial data sending end. In full duplex mode, a transmitter (including SCITX2BUF and its main register TXSHF) and a receiver (including SCIRXBUF and RXSHF) are available ). The transmitter stores the data to be sent in SCITXBUF, and shifts the data to the SCITXD pin one by one each time. When receiving the data, it moves the data on the SCIRXD pin one by one at a time, load SCIRXBUF and SCIRXEMU to read from the CPU. With a programmable baud rate generator, you can get more than 65 000 different programmable rates. SCI provides an independent interrupt request and interrupt vector for the receiver and transmitter: If RX/bkint ena bit (SCICTL2.1) is set, when SCI receives a complete frame, when the data in RXSHF is transmitted to SCIRXBUF, this action places the RXRDY sign (SCIRXST.6) and starts an interruption. If the tx int ena bit (SCICTL2.0) is set to a bit, when the data in SCITXBUF is sent to TXSHF at any time, the transmitter is determined to be interrupted, indicating that the CPU can write data to SCITXBUF. This action sets the TXRDY flag and starts an interruption.
2 hardware implementation
For standard asynchronous serial communication between TMS320C6711D and PostgreSQL, the SCI interface of postgresql can directly support this communication. You only need to configure the SCI interface to the serial interface mode through the internal special function register. In addition to configuring the serial interface through the internal special function registers, the McBSP of the TMS320C6711D should also be short-connected to the DR and FSR in the hardware design and be connected to the SCI serial data transmission pin (SCITXD). This is because the data lines in Standard Asynchronous Serial Communication contain both Frame Synchronization information and data information. The SCI serial data receiving pin (SCIRXD) is connected to the McBSP DX.
Because the interface voltages of TMS320C6711D and PostgreSQL 3.3 are both V, the two pins can be directly connected without level conversion. Figure 4 shows the Serial Asynchronous communication interface circuit between McBSP and SCI.

3. Configuration and calculation of software parameters
3.1 for tms320c6711d
(1) Calculation of baud rate
The serial clock generated inside the TMS320C6711D is determined by the system clock frequency SYSCLK and the sampling rate register. The clock frequency of MCBSP internal data, that is, the asynchronous baud rate, is determined by the following formula:
MCBSP asynchronous baud rate = sampling rate register input clock frequency/(CLKGDV + 1)
Among them: CLKGDV = sampling rate register input clock frequency/McBSP asynchronous baud rate-1.
When the sampling rate registers CLKSM = 1, the sampling rate registers input clock frequency = CPU Kernel Input clock/2;
When the sampling rate registers CLKSM = 0, the sampling rate registers input clock frequency = CPU Kernel Input clock.
In this system, the input clock of the kernel of TMS320C6711D is 150 MHz, and the CLKSM bit of the sampling rate register is set to 1. If the baud rate of McBSP asynchronous communication is 312.5kb/s, according to the above formula, the CLKGDV segment parameter of the sampling rate register should be set to 239, that is, 0xEF in hexadecimal format.
(2) Special Function register Initialization
The special function registers related to McBSP configuration in the TMS320C6711D mainly include: serial control register (SPCR), receiving control register (RCR), sending control register (XCR), and sampling rate generator register (SRGR) multi-channel control register (MCR), receive channel enabling register (RCER), send channel enabling register (XCER), pin control register (PCR ).
When the McBSP of TMS320C6711 communicates with the SCI module of postgresql, the system configures McBSP as follows: data is a single frame, one data unit per frame, and the data unit is 8 bits; data is received at the falling edge of the clock; data is sent at the rising edge; the frame synchronization signal is highly valid; after the frame synchronization is valid, transmission of the frame is started at the first clock cycle thereafter, that is, the data delay is 0, and the baud rate of asynchronous communication is 312.5kb/s.
According to the preceding control requirements, the configuration parameters of McBSP-related special function registers in the TMS320C6711D are shown in table 1.

3.2 for PostgreSQL
(1) Calculation of baud rate
The internal serial clock generated by PostgreSQL is determined by the system clock SYSCLK frequency and baud rate Selection Register. The serial communication interface uses 16-bit baud rate to select a register. The data transmission speed can be programmed in more than 65000 different ways.
The asynchronous baud rate of serial communication interfaces in different communication modes is determined by the following methods:
BRR = 1 ~ The asynchronous baud rate of the serial communication interface at 535 is:
SCI asynchronous baud rate = SYSCLK/[(BRR + 1) × 8]
Where: BRR = SYSCLK/(SCI asynchronous baud rate × 8)-1
When BRR = 0, the asynchronous baud rate of the serial communication interface is:
SCI asynchronous baud rate = SYSCLK/16
Here, BRR is equal to the baud rate and the 16-bit value of the Register is selected.
In this system, the input clock of the System of PostgreSQL is 25 MHz. If the baud rate of SCI asynchronous communication is 312.5kb/s, the baud rate should be set to 9 according to the above formula, that is, the hexadecimal 0x0009.
(2) Special Function register Initialization
The asynchronous serial communication configuration of the SCI module of postgresql includes pin configuration, communication mode configuration, and interrupt configuration. The related special function registers include Multiplexing Control registers (MCRA) port Data and direction control register (PADATDIR), serial communication interface control register 1 and 2 (SCICTL1 and SCICTL2), communication control register (SCICCR) high-byte registers, low-byte registers (sciiniud and SCILBAUD), priority control registers (SCIPRI), and receiving status registers (SCIRXST.
To implement standard asynchronous digital communication with a communication baud rate of 312.5kb/s, the SCI module should be configured as the serial communication function mode, and the special function registers should be configured as shown in table 2.

4. Software Design
In the system, the image processing result is sent to PostgreSQL by using McBSP, and the latter receives data information in response to SCI interruption. The diagram of the two software flows is shown in Figure 5.

5. Serial Communication initialization program
The difficulty in the software design of serial communication between TMS320C6711 and TMS320LF2407 is the initial program design of McBSP and SCI. The initialization program includes pin configuration, communication mode configuration, and interrupt configuration of the chip. The following are the initialization program modules of the McBSP module of TMS320C6711 and the SCI module of postgresql respectively.
(1) McBSP module initialization program of TMS320C6711
Void init_mcbsp0_master (void)
{
MCBSP_Config mcbspCfg0 =
{
0x00010001, // configure the spcr register
0x000D0000, // configure the rcr register
0x00040020, // configure the xcr register
0x200000ef, // configure the srgr register,
// Set the baud rate to 312.5kb/s.
0x00000000, // configure the MCR register
0x00000000, // configure the rCER register
0x00000000, // configure the xcer register
0x00000b0c // configure the PCR register
};

Hmcbsp0 = mcbsp_open (mcbsp_dev0, mcbsp_open_reset );
// Select Port 0
Mcbsp_config (hmcbsp0, & mcbsp1_0 );

Irq_map (irq_evt_rint0, 13); // The ing receiving interrupt 0 is
// Interrupted on the 13th
IRQ_reset (IRQ_EVT_RINT0 );
IRQ_enable (IRQ_EVT_RINT0); // enable interrupt

MCBSP_enableRcv (hMcbsp0 );
MCBSP_enableSrgr (hMcbsp0); // Handle to SRGR
MCBSP_enableFsync (hMcbsp0 );
}
(2) SCI module initialization program of postgresql
Void sci_INIT (void)
{
MCRA = MCRA | 0x0003; // set the pins SCITXD/IOPA0 and
// SCIRXD/IOPA1 for Serial Communication
PADATDIR = 0X0100; // set the PA Port as the input port
SCICTL1 = 0x13; // enables receiving and sending
SCICTL2 = 0x02; // disable sending interruption to enable receiving interruption
SCICCR = 0X07; // 8-character length, 1 stop bit, multiple idle lines
// Processor mode, no parity
Sciadeud = 0x00; // The baud rate is set to 312.5kb/s.
SCILBAUD = 0x09;
Scipri = 0x00; // receives high-priority interrupt
Scirxst = scirxst & 0xbf; // clear the SCI receiving interruption mark
Scictl1 = 0x33; // Save settings
}
Asynchronous serial data communication can be achieved using the McBSP of TMS320C6711 and the SCI of TMS320LF2407, featuring simple circuits, flexible settings, fast data transmission, reliable and stable performance. On this basis, the master-slave dual DSP data processing system can be successfully built to effectively solve the problem that the data processing capability and control capability of a Single DSP system are difficult to balance. The design scheme introduced in this article has been used in the actual application system and has been tested for a long time. Practice has proved that this design scheme is an effective multi-DSP data exchange method.