Research on the Application of tms320128in Machine Vision

Research on the Application of tms320128in Machine Vision
Source: Micro-Computer Information Author: Liu Yuan Yi Zhigang Zhang Jian Wang Juan

Contents
Before, General Machine Vision Information processing platforms mainly include (1) based on general PC
: Mainly using software for image processing and recognition, providing medium image processing and recognition capabilities, but occupying excessive CPU processing capabilities; (2) based on general DSP Chips: the advantage is that the design is simple and flexible
Active, especially suitable for the research and development of new products; (3) based on programmable FPGA: using hardware description language (VHDL), it is difficult to develop image processing algorithms with it.
Machine Vision
Image processing and recognition technology is characterized by a large amount of processed data, complex computing, high requirements for accuracy of intermediate computing results, and a large number of multiplication operations, in addition, real-time requirements for robot vision are high.
DSP features fast operation speed, high accuracy, and dedicated hardware multiplier, which can realize single-cycle multiplication and accumulative operation. Therefore, DSP is particularly suitable for applications with high real-time requirements. Where is TI
The microprocessor specifically used to process video images and speech. It features high speed and high parallel processing capability, and is very suitable for real-time image processing and recognition.

1. Introduction to TI dm64dsp
DM642
TI is the latest DSP for multimedia processing. Built on C64x
Based on the DSP core architecture, the second generation high-performance long instruction architecture developed by Texas Instruments is VelociTI.2TM. Each multiplier can execute two 16-bit times per time period.
16-bit multiplication or four 8-bit multiplication by 8-bit multiplication. The other six arithmetic logic units can be used to perform operations such as addition, subtraction, comparison, and shift of two 16-bit or eight-bit arithmetic logic units in each time period. In a parallel architecture
A maximum of eight commands can be executed in a time period. At a 2.4 billion MHz frequency, the DMPS can perform 4.8 billion 16-bit multiplication or 8-bit multiplication per second. With this powerful computing capability
Video Coding and Image processing with a high complexity and a large amount of data can perform real-time data operations, and provide related instruction sets, such as Image and Video
Processing Library), allowing developers to easily develop image or video-related products [1, 2].
2. Overall system design ideas
Because the design of Image Recognition Algorithms requires a lot of testing and analysis, it is relatively difficult to develop and debug them directly in an embedded environment. Therefore, this paper develops Image Recognition Algorithms Based on DSP, the overall design concept and development steps are visual processing algorithms first verified and implemented on the PC platform, and then transplanted to the DSP Platform for optimization.
2.1 system hardware structure design
Ben
The principle of hardware platform system 1 is shown in the following figure: the camera uses a common PAL Color Camera, the decoding chip uses TVP5150, and the external expansion of 2 SDRAM with a size of 4MX32. External Expansion
The FLASH size is 4MX8 bit; RS-232 level conversion chip TL16C752BPT; TVP5150A is a kind of Ultra-Low Power NTSC/PAL/SECAM
Video decoding chip, NTSC/PAL/SECAM can be converted into 8-bit ITU-R BT.656 format [3, 4].

Figure 1 system hardware schematic

2.2 Software Process Design of the System
The following uses the house number recognition, a typical problem in machine vision, as an example to describe the application of DMPS in machine vision. The main function module 2 of the house number recognition algorithm is shown in.

Figure 2 flowchart of the software function module

3. Verification and Implementation of visual algorithms on the PC Platform
Portal
After determining the algorithm scheme, you need to verify the algorithm on the PC platform, test its actual effect, adjust relevant parameters, and make preparations for porting the algorithm to the DSP platform. This article uses the integrated development environment
Visual
C ++ makes full use of Microsoft's basic class library (MFC) to speed up development and improve development efficiency. To test the recognition algorithm, this paper develops a Test Platform Based on MFC.
Use VFW. The digital samples of the ripple Neural Network go through the Document menu, and the input values behind the training are stored in wih.txt, And the weights from the hidden layer to the output layer are stored in
Who.txt.
4. Implementation of visual recognition algorithms on DSP Platform
Based on the above algorithm verification, we can further implement the home card Recognition System Based on dm642. Depending on the differences between the PC platform and the DM642 platform, the following issues should be taken into account during program migration [5-7]:
(1) Delete or replace C functions not supported by DSP

All Codes Using MFC on the PC platform are deleted because DSP does not support any MFC classes and objects.
(2) Adjustment of variable access methods
Save programs by segments in the dm642.
Storage, including. Text,. cinit,. Switch,. BSS,. Far,. Stack,. system, etc. The C compiler of CCS supports two memory modes: Large Memory
Memory mode and small memory mode. Different memory modes affect access to. BSS segment variables. Global and static variables in the program are distributed in. BSS segments. In small memory mode, the total size cannot exceed 32 KB. Because
The global and static variables of the program have exceeded 32 KB, so the large memory mode should be adopted, that is, the compilation option should be set to-ml3.
(3) change the data type
On the PC platform, the long type is 32-bit, while the long type of DSP is 40-bit. Because the General registers of the DMPS are 32-bit, you need to read and write the two registers when accessing the 40-bit data. From the perspective of saving program running time, all the long type in the program should be changed to int32 or uint32.
(4) storage space allocation
Before allocating storage space, you must understand the size of the storage space inside and outside the chip. After compilation, the C program runs beyond the permitted access range of the storage area. In addition, you also need to pay attention to stack allocation. Check whether stack overflow occurs when the program is "running.
4.1 storage space allocation
In
In this system, the memory space includes: the second-level cache L2 of KB of dm642. some or all of the memory space can be used as the SRAM storage space, and the access speed is fast.
Storage, slow access speed. One principle of memory usage is to put data and code into the memory as much as possible. However, due to the limited memory capacity in the chip, it is often impossible to put all the data and code into the chip memory.
Key data frequently used in the process (such as the filtered template, the image binarization threshold, the image extraction threshold, and the angle of House tilt) are stored in the chip. The off-chip SDRAM mainly Stores image data (for example
Image Collection data ).
In the distribution of the system program memory, capChaAYSpace stores the Brightness Signal Y of the collected image; capChaACbSpace stores and collects
Sets the color signal Cb of the image; capChaACrSpace stores the color signal Cr of the collected image; WEIGHT stores the weights trained by the wavelet neural network; INPUT
Stores the input values of wavelet neural networks, that is, the image data after feature. tempYbuffer, tempY1buffer, and tempY2buffer mainly store the processing of various algorithm modules.
Pre-and processed data.
4.2 Implementation of system programs
The implementation part of the program mainly includes the implementation of image acquisition and image processing and recognition algorithms.
Image Acquisition
By setting the TSI (transport stream) in the video port control register (VPCTL)
The CMODE bit in the video capture channel control register (VCxCTL) to select the video capture mode. This article selects the 8-Bit ITU-R
The BT.656 capture mode is mainly used because the TVP5150 decoding chip supports the BT.656 format. This article only needs to process the Brightness Signal Y in YCbCr. Main Process of Image Acquisition
Yes: The PAL camera uses the TVP5105 decoder to generate a data stream in the BT656 format and then transmits it to the SDRAM through EDMA. The BT656 format is interlace scanning, and the actual image size of each frame
The value is 720 × 576. Each frame is divided into two parity fields. The number of lines in the odd field ranges from 0 to 288, and the number of even fields ranges from 289 to 576. To improve real-time performance, in this article, only odd-field data is retrieved, that is, the program only processes
Rows 0-28. In the recognition algorithm implementation section, this article lists the results of the image passing through each algorithm function module. The image display path is
View-> graph-> image.
The following uses the house number 523 as an example to describe various processes of DSP-based Image Processing: Acquisition of original house brand images through cameras,
The video stream adopts the BT.656 standard and performs interlace scanning. The size of each frame is 720 × 576. Here, only the odd field data is taken, that is, the size of Figure 3 (a) is 720 × 288.
There is no significant decrease in the number of images; Figure 3 (B) is a binarization image, mainly based on the histogram Information Selection threshold, with better results; Figure 3 (c) for the image after slope correction; Figure 3 (d) is normalized
After the image is enlarged, the size of the original image is 8X16, and Figure 3 (e) is the result of feature extraction, this article is mainly to extract the data in the array and then orchestrate it to facilitate
Understanding.

The experimental results show that the system recognition accuracy of a single portal card is 100%, and the recognition rate of three digital portal cards is more than 90%.
4.3 code optimization
In this article
And the recognition algorithm has the characteristics of large data volume, complex computing, and multiple dual loops. Before optimization, the system's resource utilization is low, the operation speed is slow, and far from meeting the system's real-time requirements. This article uses code optimization
Technology [8] makes the system more real-time, including developing C/C ++ code, optimizing C/C ++ code, and compiling linear assembly code.
5 conclusion
The robot vision system proposed in this article has completed the following basic functions:
(1) Implement Robot Self-positioning and target positioning in the corridor;
(2) Recognition of operators and typical obstacles can be realized in the corridor.
The innovations in this article are mainly reflected in the following two aspects:
(1) it realizes the recognition and optimization of House signs based on DSP platform, and effectively improves the recognition speed of the system's target;
(2) An autonomous robot Machine Vision System Based on Image Recognition Technology, RFID technology, and sensor technology is explored. This method effectively improves the reliability and robustness of the system.
The practical application shows that the machine vision system designed in this paper is reasonable and practical.