Research on Windows CE embedded Navigation System (Hardware Design 2)

1.1 embedded processor s3c2440a [17]

S3c2440a is a dedicated chip designed mainly for handheld devices. It features low power consumption and high-speed processing and computing capabilities. To reduce system consumption, 2440 uses the following components: 2440 Based on the ARM920T kernel, 0.13um CMOS standard unit and storage unit complex, its power consumption and small, simple, and stable design are very suitable for products with high power requirements. S3c2440a adopts the ARM920T kernel and the ARM920T structure shown in 4.1.

Figure 4.1 structure of ARM920T

The following functions are set on the s3c2440a chip;

L 1.2v kernel, 1.8 V/2.5 V/3.3v storage, 3.3v extended I/O, 16 KB instruction cache (I-Cache)/16 KB data cache (D-Cache ).

L external storage controller (SDRAM controls the cell selection logic ).

L LCD controller integrated with dedicated DMA for LCD (supports up to 4 K color STN and 256k color TFT ).

L 4 DMA controllers with external request pins.

L 3 urat (irda1.0, 64-byte tx fifo, 64 byte rx fifo ).

L 2-way SPI.

L IIC Bus Interface (supported by multiple masters ).

L IIS audio codecs interface.

L ac'97 decoder interface.

L 1.0 SD main interface, compatible with 2.11 MMC interface.

L 2-way USB Host Control/1-way USB period control (ver1.1 ).

L 4-way PWM Timer/1-way Internal timer/watchdog timer.

L 8-Channel 10-bit ADC and touch screen interface.

L RTC with Calendar function.

L camera interface (supports up to 4096x4096 input, 2048x2048 zoom input ).

L 130 General I/O and 24 external interrupt sources.

L Power Supply Control: Normal, slow, idle, sleep mode.

L on-chip clock generator with PLL.

Clock Circuit 1.2

S3c2440a has two-way clock input: one is used for CPU clock, and the other is provided to the RTC circuit. The first channel uses a 12 m crystal oscillator input into the arm, and then the internal PLL circuit of the chip makes the fclk = 400 MHz, hclk = 136 MHz, pclk = 68 MHz, and fclk is used for the CPU core, hclk is used for AHB Bus devices (such as SDRAM), pclk is used for APB bus devices (such as UART), and RTC clock circuit uses a 32.768 kHz crystal oscillator. 4.2.

Figure 4.2 Clock Circuit

1.3 Power Supply Circuit

This system involves three types of voltages. the kernel and I/O of s3c2440a are separately supplied. The operating I/O voltage is 3.3 V, and the operating voltage of the kernel is 1.25 v, the memory chip and reset chip that are directly connected to the processor also use 3.3 V power, and the peripheral circuit uses 5 V power. Based on different power supply voltages, the system uses two as1117 series low voltage differential DC regulator chips to convert 5 v dc power supply into 1.25 V and 3.3 V for the processor and other circuits. Figure 4.3 shows the schematic diagram of the power supply circuit.

Figure 4.3 schematic diagram of Power Supply Circuit

Design of Ethernet interface circuit 1.4

In embedded devices, Ethernet interfaces have become indispensable standard interfaces. Ethernet interfaces can achieve high-speed data transmission and provide many functions. S3c2440a does not provide a dedicated Ethernet MAC interface. We have adopted the dm9000 Ethernet controller produced by davicom and mounted it on the data and address bus of s3c2440a for expansion. The hardware connection between s3c2440a and dm9000 is shown in Figure 3.11. The dm9000 is accessed and controlled through the data cable [15. 0], address bus ADDR [2], and h1102 chips.

Figure 4.4 Ethernet Circuit

Interface Circuit Design of 1.5 SD/mmccard

In the navigation system, a large amount of spatial and geographic information needs to be stored. Both the CF card and SD card are suitable storage devices. In this system, SD card is selected as the storage device. The internal structure of the SD card is 3.9, and its size is 24mm × 32mm × 2.1mm. The SD card integrates the SanDisk flash memory card control and MLC (multilevel cell) technology and Toshiba (Toshiba) 0.16u and 0.13u NAND technology. It is connected to a dedicated drive through the 9-pin interface.

Data Line dat0 ~ Dat3 is used as the input when power-on is enabled. It is used as the data line after the set_bus_width command is set. Pin 1 is used as the input after power-on. The SD card uses a dedicated slot interface, and s3c2440a has a dedicated SD/MMC interface connection. You only need to connect the SD interface line of s3c2440a to the pin corresponding to the SD card. The pull-up resistance is added for the data line. The circuit connection diagram is shown in Figure 4.5.

Figure 4.5 SD/MMC Interface Circuit

1.6 Touch Screen Interface Design

Because the touch screen is durable, fast to respond, space-saving, and easy to communicate, we choose the touch screen as the main input device in the embedded vehicle navigation system. As long as you touch the graphic or text on the display with your fingers, you can perform operations on the host, making human-computer interaction more straightforward.

When the touch screen is working, you must first touch the touch screen installed on the front end of the display with your fingers or other objects, and then the system positions and selects information input based on the touch icon or menu position. The Touch Screen consists of a touch detection component and a touch screen controller. The Touch detection component is installed in front of the display screen to detect the position of the user's touch and send it to the touch screen controller. The touch screen controller is mainly used to receive the touch information from the touch point detection device, it is converted into contact coordinates and sent to the processor. At the same time, the touch screen controller can also receive and execute control commands sent from the processor. According to the working principle of the touch screen and the media for transmitting information, the commonly used touch screen is divided into four types: resistance type, Capacitive inductance type, infrared type and Surface Acoustic type. The resistive touch screen features simple structure, low cost, good light transmission effect, and completely isolated working environment from the outside, without fear of dust and water vapor. It also features high resolution, high-speed transmission and response, one-time correction, and high stability, non-Drifting features. Therefore, the system uses a resistive touch screen. The essence of the resistive touch screen is to measure the resistance partial pressure of X and Y, use a common A/D converter or A/D integrated on an embedded processor chip to measure the touch screen.

Figure 4.6 LCD circuit diagram

The S3C2440 tablet is integrated with a touch screen controller to control the four-wire resistive touch screen. In this system, X and Y data are directly obtained from the LCD, and are directly transferred to the S3C2440 chip through tsxm and tsym for processing. Then, tsxp and tsyp are directly output, circuit Diagram 4.6.

1.7 SDRAM interface circuit design

The s3c2440a chip comes with 4-byte SRAM. When complicated applications or embedded operating systems are used, 4 k ram space is far from enough. Therefore, Ram needs to be extended. SDRAM is the abbreviation of synchronous dynamic RAM. The emergence of Synchronization Technology in Dynamic Storage enables the read/write speed to change from 60ns ~ 70ns upgraded to the current 6ns ~ 7ns, increased by nearly 10 times. SDRAM features high capacity, fast access, and low cost. It is mainly used to store Execution Code and variables, and is the main memory for access operations after the system is started. For applications that require large-capacity storage, SDRAM can provide very high cost effectiveness. In this system, we have extended two 32 m × 16 bit SDRAM chips, hy57v561620, to form the system's external data storage space, as shown in 4.7.

Figure 4.7 SDRAM interface circuit

The data bus of the hy57v561620 chip is 16 bits, so we used two pieces of SDRAM chip to expand to 32 bits to cooperate with the data bus of the 32 bits of sc2440a. S3c2440a data bus data [15 .. 0], data [31 .. 16] Data Bus DQ connected to two SDRAM chips [15 .. 0]; low 13-bit address bus ADDR [14 .. 2] a [12 .. 0] pin for row and column scanning, addr25 and addr24 are connected to the BA1 and ba0 pins of the SDRAM chip respectively for storage block selection. The chip signal line/cs of the SDRAM is connected to the ngcs6 pin of the s3c2440a chip. The write enable pin of the SDRAM chip we is connected to the nwe pin of the S3C2410A chip, and the line/column address signal line ras and/CAS are respectively connected to the nsras and nscas pins of the s3c2440a chip, the clock enable signal/cke connects to the scke pin of the s3c2440a chip.