RTL behavior-level simulation, comprehensive BackDoor-level functional simulation, and timing simulation

In digital circuit designSource codeInput, synthesis, and implementation are three major stages, and the starting point of circuit simulation is also basically consistent with those stages, simulation can be divided into RTL behavior-level simulation, integrated BackDoor-level functional simulation, and time series simulation based on the applicable design stages. This simulation profile model is not only suitable for FPGA/CPLD design, but also for icdesign ....
I. RTL behavior-level simulation
The first simulation executed in most designs will be RTL behavior-level simulation. Simulation at this stage can be used to checkCodeThe syntax errors and code behaviors are correct, excluding the delay information. If some special underlying components related to the device are not instantiated, the simulation at this stage can also be unrelated to the device. Therefore, in the initial stage of design, without using special underlying components, the code can be improved in readability and maintainability, and the simulation efficiency can be improved and easily reused. (Most designers call functional simulation at this stage !)

 

2. Integrated BackDoor-level function simulation (front simulation)
Generally, the second simulation in the design process is a comprehensive BackDoor-level functional simulation. In addition to a standard network Table file, the vast majority of integrated tools can also output network-based table learning language, it cannot be used for simulation, but the output network table of OpenGL or VHDL can be used for simulation, the reason for the door-level simulation is that the simulation network table provided by the integrated tool already corresponds to the underlying component model of the device of the manufacturer, therefore, in order to perform integrated simulation, you must add the device library of the manufacturer during the simulation process and perform some necessary configurations on the simulator. Otherwise, the simulator will not know the underlying components and cannot perform simulation. Xilinx's integrated development environment ise does not support integrated post-simulation, but instead uses frontend-level simulation ing. For the Xilinx development environment, there is little difference between the two simulations.

III. Timing simulation (post-simulation)
the last simulation in the design process is timing simulation. A time series simulation model can be provided after the design layout and wiring are completed. This model also contains some information about the device and provides a standard delay format timing anotation file ). The SDF time series annotation was originally used in the design of the OpenGL language. This concept is also referenced in the design of the VHDL language. The average designer does not need to know the SDF