S3C2410 clock signal: fclk, hclk, and pclk

S3C2410 has three clock types: flck, hclk, and pclk (these three clock types are core clock types) The S3C2410 chip has such a paragraph: FclkIs used by ARM920T,Kernel clock, clock speed. HclkIs used for AHB Bus, which is used by the ARM920T, the memory controller, the interrupt controller, the LCD controller, the DMA and USB Host block. That isProvides clock signals for peripherals on the AHB Bus, including USB clock.
AHB Bus is used to connect high-speed peripherals. PclkIs used for APB bus, which is used by the peripherals such as wdt, IIS, I2C, PWM timer, MMC interface, ADC, UART, gpio, RTC and SPI. That isProvides clock signals for peripherals on the APB bus, that is, the I/O interface clock. The serial clock settings are from pclk. APB bus is used to connect low-speed peripherals. The S3C2410X supports selection of dividing ratio Fclk, Hlck and pclk. This ratio is determined by hdivn and pdivn of clkdivn control register. S3C2410 can be changed by setting the hdivn bit (1st bits) and pdivn bit (0th bits) of the clkdivn control register. Fclk, Hlck and pclk ratio. How to obtain FclkWhat is the clock frequency of hlck and pclk? You can first obtain a CLK struct through clk_get

 
/* Clk_get get a clock named ID * input parameter Dev: Can be null * input parameter ID: clock name, such as fclk, hclk, pclk * return value: returns the CLK struct of the clock */struct CLK * clk_get (struct device * Dev, const char * ID) struct CLK {struct list_head list; struct module * owner; struct CLK * parent; const char * Name;/* The Clock name/int id; int usage; unsigned long rate;/* clock frequency/unsigned long ctrlbit; int (* enable) (struct CLK *, int enable); int (* set_rate) (struct CLK * C, unsigned long rate); unsigned long (* get_rate) (struct CLK * C); unsigned long (* round_rate) (struct CLK * C, unsigned long rate); int (* set_parent) (struct CLK * C, struct CLK * parent );};
 

Then pass the CLK struct returned by clk_getClk_get_rate: gets the clock frequency. Prototype: Unsigned long clk_get_rate (struct CLK * CLK); Let's look at an example:

 
Printk (kern_debug "fclk = % d, pclk = % d, hclk = % d, uclk = % d \ n", clk_get_rate (clk_get (null, "fclk ")), clk_get_rate (clk_get (null, "hclk"), clk_get_rate (clk_get (null, "pclk"), clk_get_rate (clk_get (null, "uclk ")));
 

another uclk clock exists here, providing clock signals to USB. Uclk is an external clock source. It is introduced by gph8/uclk pins of the S3C2410 chip to provide external clock signals for UART to obtain more accurate clock frequencies. about AMBA On-Chip Bus
AMBA (advanced microcontroller Bus Architecture) it is an on-chip bus specification proposed by arm. The AMBA 2.0 specification consists of four parts: AHB (AMBA High Performance Bus), ASB (AMBA System Bus), APB (AMBA Peripheral Bus), and test methodology.
the advanced high-performance bus (AHB) is used to connect high-performance, high-clock system modules (such as CPU, DMA, and DSP) it forms a high-performance system backbone bus (back-bone Bus ). The peripherals on the AHB Bus have LCD controller (cont stands for controller and controller) USB Host cont, extmaster, Nand cont, nand flash Boot Loader, bus cont, interrupt cont, power management, memory
cont (SRAM/NOR/SDRAM, etc ). the advanced system bus (ASB) is the first generation of AMBA system bus. Compared with AHB, the data width is smaller. It supports 8-bit, 16-bit, and 32-bit typical data widths. the Advanced Peripheral Bus (APB) is a local secondary bus ), connect to AHB/ASB through the bridge. It is mainly used to interconnect devices that do not require high-performance pipeline interfaces or high-bandwidth interfaces. Peripherals on APB bus include UART, USB device, SDI/MMC, Watch Dog Timer, bus cont, SPI, IIC, IIS, gpio, RTC, ADC, Timer/PWM.

Source: http://l301l.blog.163.com/blog/static/1050584542010101295948273/